Non-volatile memory and method with improved sensing having bit-line lockout control
First Claim
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1. A method of sensing a group of nonvolatile memory cells in parallel, comprising:
- (a) providing access to individual memory cells of the group by associated bit lines and a common word line;
(b) selecting a demarcation threshold voltage level relative to which the sensing is to be performed, the demarcation threshold voltage level being one among a set of multiple threshold voltage levels;
(c) sensing, in a predetermined number of more than one sensing pass, the group of memory cells in parallel relative to the selected demarcation threshold voltage,wherein whenever in less than all of said predetermined number of more than one sensing pass, a condition for bit-line lockout by grounding the bit-line is enabled, performing (d1) to (d2) before proceeding to (e), otherwise skipping to (e);
(d1) identifying any memory cell sensed to have a threshold voltage level less than the selected demarcation threshold voltage level;
(d2) locking out the associated bit line of any identified memory cell by setting the associated bit line to a ground potential, said locking out being performed selectively for less than all iterations of the voltage levels from the set of multiple threshold voltage levels, whenever an enabling condition for bit-line lockout is satisfied; and
(e) repeating (b) to (e) for a next voltage level from the set of multiple threshold voltage levels until every voltage level from the set has been iterated.
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Abstract
In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.
415 Citations
28 Claims
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1. A method of sensing a group of nonvolatile memory cells in parallel, comprising:
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(a) providing access to individual memory cells of the group by associated bit lines and a common word line; (b) selecting a demarcation threshold voltage level relative to which the sensing is to be performed, the demarcation threshold voltage level being one among a set of multiple threshold voltage levels; (c) sensing, in a predetermined number of more than one sensing pass, the group of memory cells in parallel relative to the selected demarcation threshold voltage, wherein whenever in less than all of said predetermined number of more than one sensing pass, a condition for bit-line lockout by grounding the bit-line is enabled, performing (d1) to (d2) before proceeding to (e), otherwise skipping to (e); (d1) identifying any memory cell sensed to have a threshold voltage level less than the selected demarcation threshold voltage level; (d2) locking out the associated bit line of any identified memory cell by setting the associated bit line to a ground potential, said locking out being performed selectively for less than all iterations of the voltage levels from the set of multiple threshold voltage levels, whenever an enabling condition for bit-line lockout is satisfied; and (e) repeating (b) to (e) for a next voltage level from the set of multiple threshold voltage levels until every voltage level from the set has been iterated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A nonvolatile memory, comprising:
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an array of memory cells accessible by bit lines and word lines; a group of sensing circuits for sensing conduction currents in a corresponding group of memory cells in parallel wherein individual memory cells of the group as accessible by associated bit lines and a common word line; a word line voltage supply for precharging the common word line to a selected demarcation threshold voltage level relative to which the sensing is to be performed, the demarcation threshold voltage level being one among a set of multiple threshold voltage levels; a bit line voltage supply for precharging the associated bit line substantially to a predetermined voltage level; a set of control signals for controlling the group of sensing circuits to sense the group of memory cells in parallel relative to the selected demarcation threshold voltage in a predetermined number of more than one pass; and a bit-line grounding circuit for each sensing circuit to ground the associated bit line responsive to both a sense result of said each sensing circuit and a control signal which is enabled for bit-line lockout during sensing for less than all of said predetermined number of more than one sensing pass. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification
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Current AssigneeSanDisk Technologies LLC (Western Digital Corporation)
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Original AssigneeSandisk Technologies Incorporated (Western Digital Corporation)
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InventorsMokhlesi, Nima
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Primary Examiner(s)Hoang; Huan
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Application NumberUS12/897,089Publication NumberTime in Patent Office386 DaysField of Search365/185.21, 365/185.22, 365/185.03, 365/185.18, 365/185.25US Class Current365/185.21CPC Class CodesG11C 16/26 Sensing or reading circuits...
