Microcontroller, control system and design method of microcontroller
First Claim
1. A microcontroller comprising:
- a first data processing unit operated in synchronization with a first clock signal;
a circuit unit operated in synchronization with the first clock signal based on a control of the first data processing unit;
a second data processing unit performing the same data processing as the first data processing unit with a delay from the first data processing unit for an identical process in synchronization with a second clock signal having the same cycle as the first clock signal;
a first interface circuit having a plurality of flip flops for holding a first signal outputted from the first data processing unit to the circuit unit;
a comparator which compares a second signal outputted from the second data processing unit in response to an output of the first signal by the first data processing unit and the signal held in the first interface circuit in synchronization with the second clock signal; and
a second interface circuit having a plurality of flip flops for holding a third signal supplied from the circuit unit to the first data processing unit and outputting the same to the second data processing unit,wherein the plurality of flip flops in the first and second interface circuits include those using the first clock signal for defining a latch timing and those using the second clock signal for the same.
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Abstract
Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.
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Citations
12 Claims
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1. A microcontroller comprising:
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a first data processing unit operated in synchronization with a first clock signal; a circuit unit operated in synchronization with the first clock signal based on a control of the first data processing unit; a second data processing unit performing the same data processing as the first data processing unit with a delay from the first data processing unit for an identical process in synchronization with a second clock signal having the same cycle as the first clock signal; a first interface circuit having a plurality of flip flops for holding a first signal outputted from the first data processing unit to the circuit unit; a comparator which compares a second signal outputted from the second data processing unit in response to an output of the first signal by the first data processing unit and the signal held in the first interface circuit in synchronization with the second clock signal; and a second interface circuit having a plurality of flip flops for holding a third signal supplied from the circuit unit to the first data processing unit and outputting the same to the second data processing unit, wherein the plurality of flip flops in the first and second interface circuits include those using the first clock signal for defining a latch timing and those using the second clock signal for the same. - View Dependent Claims (2, 3, 4, 9, 10, 11, 12)
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5. A control system for controlling an automotive powertrain system, the control system comprising:
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a control circuit; a sensor having an output connected to the control circuit; and an actuator whose operation is controlled by the control circuit, wherein the control circuit includes; a first data processing unit operated in synchronization with a first clock signal; a circuit unit operated in synchronization with the first clock signal based on a control of the first data processing unit; a second data processing unit performing the same data processing as the first data processing unit with a delay from the first data processing unit for an identical process in synchronization with a second clock signal having the same cycle as the first clock signal; a first interface circuit having a plurality of flip flops for holding a first signal outputted from the first data processing unit to the circuit unit; a comparator which compares a second signal outputted from the second data processing unit in response to an output of the first signal by the first data processing unit and the signal held in the first interface circuit in synchronization with the second clock signal; and a second interface circuit having a plurality of flip flops for holding a third signal supplied from the circuit unit to the first data processing unit and outputting the same to the second data processing unit, and wherein the plurality of flip flops in the first and second interface circuits include those using the first clock signal for defining a latch timing and those using the second clock signal for the same. - View Dependent Claims (6, 7, 8)
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Specification