Apparatus and method for using a page buffer of a memory device as a temporary cache

• US 8,046,527 B2
• Filed: 02/12/2008
• Issued: 10/25/2011
• Est. Priority Date: 02/22/2007
• Status: Expired due to Fees

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki, Oh, HakJune, Pyeon, Hong Beom
• Primary Examiner(s): Dudek, Jr.; Edward J
• Application Number:
  US12/029,634
• Publication Number:
  US 20080205168A1
• Time in Patent Office: 1,351 Days
• Field of Search: 711/103, 711/118, 711/154, 711/E12.002, 710/52
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4247 on a daisy chain bus

Abstract

An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller'"'"'s local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.

Claims

1. A method for communicating with a serial interconnection of a plurality of memory devices connected in-series, at least one of the memory devices having a temporary store element and a device identification associated with an address in the serial interconnection, the method comprising:

sending a write command including a device identification, a write operation instruction and data stored in a data storage to the serial interconnection, the plurality of memory devices being configured to propagate the write command therethrough in response to a propagation control,

at the at least one of the memory devices,

determining whether it is selected based on the device identification included in the write command and the associated device identification, in a case of determination where the memory device is selected, a selection determination for writing being provided,

writing the data to the temporary store element of the memory device in response to the selection determination for writing and the write operation instruction;

at a later time, sending a read command including a device identification and a read operation instruction to the serial interconnection, the plurality of memory devices being configured to propagate the read command therethrough in response to the propagation control,

at the at least one of the memory devices,

determining whether it is selected based on the device identification included in the read command and the associated device identification, in a case of determination where the memory device is selected, a selection determination for reading being provided,

reading the data written to the temporary store element of the memory device in response to the selection determination for reading and the read instruction, the read data being provided through the serial interconnection to the data storage.

2. The method of claim 1 further comprising

storing the data provided from the memory device responded to the selection determination for reading to the data storage.

3. The method of claim 2 further comprising:

freeing up space storing the data in the data storage after performing the step of sending the write command.

4. The method of claim 1 wherein:

at the at least one of the memory devices

the step of determining comprises determining whether the device identification included in the write command matches the associated device identification, in a case of device identification matching, the selection determination for writing being provided,

the step of determining comprises at the later time comprises determining whether the device identification included in the read command matches the associated device identification, in a case of device identification matching, the selection determination for reading being provided.

5. The method of claim 1 wherein the propagation control comprises first and second enable signals, at each of the memory devices,

the first enable signal enabling the memory device to respond to the received write command or the received read command;

and

the second transfer enable signal enabling the memory device to transfer the received write command or the received read command to another memory device of the serial interconnection.

6. The method of claim 1 further comprising:

freeing up space storing the data in the data storage after performing the step of sending the write command; and

after performing the step of freeing, storing the data provided from the memory device responded to the selection determination for reading to the data storage.

7. A system comprising:

a serial interconnection of a plurality of memory devices connected in-series, each of the memory devices having a temporary store element and a device identification associated with an address in the serial interconnection; and

an apparatus for communicating with the plurality of memory devices, the apparatus comprising a data storage and a processor for

sending a write command including a device identification, a write operation instruction and data stored in the data storage to the serial interconnection, the plurality of memory devices being configured to propagate the write command therethrough in response to a propagation control; and

at a later time, sending a read command including a device identification and a read operation instruction to the serial interconnection, the plurality of memory devices being configured to propagate the write command therethrough in response to the propagation control,

each of the plurality of memory devices being configured

to determine whether it is selected based on the device identification included in the write command and the associated device identification, in a case of determination where the memory device is selected, a selection determination for writing being provided,

the data being written to the temporary store element of the memory device in response to the selection determination for writing and the write operation instruction included in the write command,

to determine whether it is selected based on the device identification included in the read command and the associated device identification, in a case of determination where the memory device is selected, a selection determination for reading being provided,

the data written to the temporary store element of the memory device being read in response to the selection determination for reading and the read operation instruction included in the read command, the read data being provided through the serial interconnection to the apparatus.

8. The system of claim 7 wherein the processor is configured to free up space in the data storage of the apparatus upon sending the write command to the serial interconnection.

9. The system of claim 8 wherein:

the processor is further configured to store the read data into the data storage of the apparatus upon receiving the data provided from the memory device that responded to the determination selection for reading.

10. The system of claim 7 wherein each of the plurality of memory devices is a non-volatile memory device.

11. The system of claim 10 wherein the non-volatile memory device comprises a NAND flash device.

12. The system of claim 11 wherein the NAND flash device has a page buffer as the temporary store element for temporary storing information on data.

13. The system of claim 7 wherein each of the memory devices is configured:

to determine whether the device identification included in the write command matches the associated device identification, in a case of device identification matching, the selection determination for writing being provided; and

to determine whether the device identification included in the read command matches the associated device identification, in a case of device identification matching, the selection determination for reading being provided.

14. The system of claim 7 wherein each of the memory devices further has a first input for receiving the write command and receiving the read command at the later time.

15. The system of claim 14 wherein each of the memory devices further has second and third inputs for receiving first and second enable signals, respectively,

the first enable signal enabling the memory device to respond to the received write command or the received read command,

the second enable signal enabling the memory device to transfer the received write command or the received read command to another memory device of the serial interconnection.