Low power decompression of test cubes
First Claim
1. One or more computer-readable media storing a compressed test pattern, the compressed test pattern including compressed test pattern values that cause a decompressor to produce identical output values over two or more decompressor clock cycles, the output values including at least some values that target a selected fault in an integrated circuit design.
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Accused Products
Abstract
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
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Citations
17 Claims
- 1. One or more computer-readable media storing a compressed test pattern, the compressed test pattern including compressed test pattern values that cause a decompressor to produce identical output values over two or more decompressor clock cycles, the output values including at least some values that target a selected fault in an integrated circuit design.
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4. A method of generating a test pattern for testing a circuit-under-test,
comprising: -
inputting compressed test pattern bits into one or more decompressor inputs during two or more clock cycles; and outputting decompressed test pattern bits from two or more decompressor outputs during the two or more clock cycles, wherein each respective decompressor output outputs identical decompressed test pattern bits during the two or more clock cycles, and wherein only a portion of the decompressed test pattern bits output from the two or more decompressor outputs are specified test pattern bits that target one or more faults in the circuit-under-test. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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- 11. One or more computer-readable media storing a compressed test pattern, the compressed test pattern including compressed test pattern values that cause a decompressor to produce identical output values over two or more decompressor clock cycles, the output values including at least some values that target a selected fault in an integrated circuit design, wherein the compressed test pattern values comprise a first set of compressed test pattern values, wherein the identical output values comprise a first set of identical output values, and wherein the two or more decompressor clock cycles comprise a first set of decompressor clock cycles, the compressed test pattern further including a second set of compressed test pattern values that causes the decompressor to produce a second set of identical output values over two or more different consecutive decompressor clock cycles.
Specification