Method and system to emulate an M-bit instruction set

• US 8,046,748 B2
• Filed: 07/25/2005
• Issued: 10/25/2011
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cabillic, Gilbert, Chauvel, Gerard, Lesot, Jean-Philippe
• Primary Examiner(s): Khatri; Anil
• Application Number:
  US11/188,310
• Publication Number:
  US 20060025986A1
• Time in Patent Office: 2,283 Days
• Field of Search: 717/127, 717134-143, 717/131
• US Class Current: 717/138
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a table to an index location (the index location based on the at least a portion of the instruction), executing a first series of instructions directly executable by the processor (the first series of instructions pointed to by the table at the index location), and thereby emulating execution of the instruction from the first instruction set.

Claims

1. A method comprising:

fetching at least a first portion of an instruction, the instruction from a first instruction set that is not directly executable by a processor;

indexing into a table to an index location, the index location based on the at least a portion of the instruction;

executing a first series of instructions, the first series of instructions from a second instruction set directly executable by the processor, the first series of instructions pointed to by the table at the index location, wherein executing the first series of instructions further comprises fetching a second portion of the instruction, and triggering execution of a second series of instructions; and

thereby

emulating execution of the instruction from the first instruction set.

2. The method as defined in claim 1 further comprising:

wherein fetching further comprises fetching M bits of the instruction having N bits, where N is greater than M;

wherein executing further comprises executing the first and second series of instructions, each of the first and second series of instructions from an instruction set of M bits or less.

3. A processor comprising:

an instruction fetch logic;

a decode logic coupled to the instruction fetch logic;

wherein the processor fetches, decodes and directly executes instructions from a first instruction set comprising M number of bits and a second instruction set; and

wherein the processor emulates executing instructions from a third instruction set using the first instruction set, each instruction of the third instruction set comprising N number of bits with N less than or equal to M.

4. The processor as defined in claim 3 further comprising:

a vector table associated with the decode logic;

wherein the processor, when emulating execution of instructions from the third instruction set, uses instructions from the third instruction set as a reference to a portion of the vector table, which vector table is configured to contain a pointer to one or more instructions directly executable by the processor to emulate execution of each instruction.

5. The processor as defined in claim 3 wherein the first instruction set is a register-based instruction set, the second instruction set is a stack-based instruction set, and M equals eight (8).

6. The processor as defined in claim 5 wherein the second instruction set is Java bytecodes.

7. The processor as defined in claim 3 wherein each instruction in the first instruction set comprise M number of bits, and wherein each instruction of the third instruction set comprises N number of bits with N greater than M.

8. The processor as defined in claim 7 further comprising:

a vector table associated with the decode logic;

wherein the processor, emulating execution of instructions from the third instruction set, uses a first portion of an instruction from the third instruction set as a reference to a portion of the vector table, which vector table is configured to contain a pointer to a first series of instructions directly executable by the processor; and

wherein the first series of instructions directly executable by the processor are configured to obtain a second portion of the instruction of the third instruction set, and wherein the series of instructions are further configured to trigger execution of a second series of instructions directly executable by the processor to emulate execution of the instruction of the third instruction set.

9. The processor as defined in claim 7 wherein the first instruction set is a register-based instruction set, the second instruction set is a stack-based instruction set, and M equals eight (8).

10. The processor as defined in claim 9 wherein the second instruction set is Java bytecodes.

11. A device comprising:

a first processor;

a memory coupled to the first processor;

a second processor coupled to the first processor and the memory;

wherein the second processor fetches, decodes, and directly executes instructions from a first instruction set, and fetches, decodes, and directly executes instructions from a second instruction set; and

wherein the second processor emulates executing instructions from a third instruction set using the first instruction set.

12. The device as defined in claim 11 wherein each instruction in the first instruction set comprises M number of bits, and wherein the each instruction of the third instruction set comprises N number of bits with N less than or equal to M.

13. The device as defined in claim 12 further comprising:

a vector table associated with the second processor;

wherein the second processor, when emulating execution of instructions from the third instruction set, uses instructions from the third instruction set as a reference to a portion of the vector table, which vector table is configured to contain a pointer to one or more instructions directly executable by the second processor to emulate execution of each instruction.

14. The device as defined in claim 12 wherein the first instruction set is a register-based instruction set, the second instruction set is a stack-based instruction set, and M equals eight (8).

15. The device as defined in claim 14 wherein the second instruction set is Java byte codes.

16. The device as defined in claim 11 wherein each instruction in the first instruction set comprise M number of bits, and wherein the each instruction of the third instruction set comprises N number of bits with N greater than M.

17. The device as defined in claim 16 further comprising:

a vector table associated with the second processor;

wherein the second processor, emulating execution of instructions from the third instruction set, uses a first portion of an instruction from the third instruction set as a reference to a portion of the vector table, which vector table is configured to contain a pointer to a first series of instructions directly executable by the second processor; and

wherein the first series of instructions directly executable by the second processor are configured to obtain a second portion of the instruction of the third instruction set, and wherein the series of instructions are further configured to trigger execution of a second series of instructions directly executable by the second processor to emulate execution of the instruction of the third instruction set.

18. The device as defined in claim 16 wherein the first instruction set is a register-based instruction set, the second instruction set is a stack-based instruction set, and M equals eight (8).