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Vertical MOS transistor and method therefor

  • US 8,048,740 B2
  • Filed: 12/03/2009
  • Issued: 11/01/2011
  • Est. Priority Date: 07/13/2007
  • Status: Active Grant
First Claim
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1. A method of forming a vertical MOS transistor comprising:

  • providing a semiconductor substrate of a first conductivity type having a first surface and a second surface;

    forming a first doped region of a second conductivity type on the first surface of the semiconductor substrate and extending into the semiconductor substrate;

    forming a drain conductor on the second surface of the semiconductor substrate;

    forming source regions and gate regions of the vertical MOS transistor extending into the first doped region wherein the vertical MOS transistor is devoid of a field oxide region overlying an interface between the semiconductor substrate and an outside edge of the first doped region wherein a portion of the interface extends toward the first surface of the semiconductor substrate;

    forming a thin dielectric overlying the portion of the interface of the semiconductor substrate and the outside edge of the first doped region;

    forming an inner-layer dielectric overlying the thin dielectric and overlying at least the portion of the interface; and

    forming a gate conductor on a first portion of the thin insulator and positioned between the outside edge of the first doped region and the gate regions.

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