Vertical MOS transistor and method therefor

• US 8,048,740 B2
• Filed: 12/03/2009
• Issued: 11/01/2011
• Est. Priority Date: 07/13/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Venkatraman, Prasad
• Primary Examiner(s): Stark; Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US12/630,621
• Publication Number:
  US 20100078717A1
• Time in Patent Office: 698 Days
• Field of Search: 438/268, 257/60, 257/135, 257/263, 257/330
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor.

Claims

1. A method of forming a vertical MOS transistor comprising:

providing a semiconductor substrate of a first conductivity type having a first surface and a second surface;

forming a first doped region of a second conductivity type on the first surface of the semiconductor substrate and extending into the semiconductor substrate;

forming a drain conductor on the second surface of the semiconductor substrate;

forming source regions and gate regions of the vertical MOS transistor extending into the first doped region wherein the vertical MOS transistor is devoid of a field oxide region overlying an interface between the semiconductor substrate and an outside edge of the first doped region wherein a portion of the interface extends toward the first surface of the semiconductor substrate;

forming a thin dielectric overlying the portion of the interface of the semiconductor substrate and the outside edge of the first doped region;

forming an inner-layer dielectric overlying the thin dielectric and overlying at least the portion of the interface; and

forming a gate conductor on a first portion of the thin insulator and positioned between the outside edge of the first doped region and the gate regions.

3. The method of claim 1 wherein forming source regions and gate regions of the vertical MOS transistor includes forming the gate regions as trench type gates extending from the first surface of the semiconductor substrate into the first doped region and forming a source region adjacent to a trench type gate.

4. The method of claim 1 wherein forming source regions and gate regions of the vertical MOS transistor includes forming the thin insulator on the first surface of the semiconductor substrate and overlying the interface between the semiconductor substrate and the outside edge of the first doped region.

5. The method of claim 4 further including forming the gate conductor to not extend to overlie the interface between the semiconductor substrate and the outside edge of the first doped region.

6. The method of claim 4 further including forming the inner-layer dielectric on the first portion of the thin insulator and to overlie a portion of the gate conductor.

8. The method of claim 1 wherein forming the gate conductor includes forming the gate conductor material overlying the portion of the interface that extends toward the first surface.

9. The method of claim 1 further including forming a source conductor forming an electrical connection to the source regions but not forming an electrical connection to the gate conductor.

2. A method of forming a vertical MOS transistor comprising:

providing a semiconductor substrate of a first conductivity type having a first surface and a second surface;

forming a first doped region of a second conductivity type on the first surface of the semiconductor substrate and extending into the semiconductor substrate;

forming a drain conductor on the second surface of the semiconductor substrate; and

forming source regions and gate regions of the vertical MOS transistor extending into the first doped region wherein the vertical MOS transistor is devoid of a thermally grown field oxide region overlying a portion of an interface between the semiconductor substrate and an outside edge of the first doped region wherein the portion of the interface extends toward the first surface of the semiconductor substrate.

7. A method of forming a vertical MOS transistor comprising:

providing a semiconductor substrate of a first conductivity type having a first surface and a second surface;

forming a first doped region of a second conductivity type on the first surface of the semiconductor substrate and extending into the semiconductor substrate including forming an interface between the semiconductor substrate and the first doped region with a portion of the interface extending toward the first surface of the semiconductor substrate;

forming a drain conductor on the second surface of the semiconductor substrate; and

forming source regions and gate regions of the vertical MOS transistor extending into the first doped region wherein the vertical MOS transistor is devoid of a field oxide region overlying the portion of the interface between the semiconductor substrate and the outside edge of the first doped region.