Integrated circuit on high performance chip

• US 8,048,766 B2
• Filed: 06/23/2004
• Issued: 11/01/2011
• Est. Priority Date: 06/24/2003
• Status: Expired due to Fees

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Ulmer, Laurent, Parat, Guy, Joly, Jean-Pierre
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US10/561,299
• Publication Number:
  US 20060252229A1
• Time in Patent Office: 2,687 Days
• Field of Search: 438/455, 438/456, 257/618, 257/528, 257/531, 257/532
• US Class Current: 438/455
• CPC Class Codes: B81C 1/00253 Processes for integrating an electronic processing unit with a micromechanical structure not provided for in B81C1/0023 - B81C1/00246
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.

Claims

1. A method of fabricating a die containing an integrated circuit comprising active components and passive components, at least a part of the passive components comprising critical passive components, the method comprising:

producing a first substrate including at least one active component including heating the first substrate at a temperature lower than a first temperature above which the first substrate is unacceptably degraded;

producing a second substrate including the critical passive components including heating the second substrate at a temperature higher than the first temperature;

bonding the first and second substrates, wherein the bonding comprises performing a layer transfer; and

after bonding of the first and second substrates, producing at least one interconnection line between the components of the first and second substrates, the interconnection line passing through the second substrate.

2. A method according to claim 1, wherein the at least one active component comprises transistors.

3. A method according to claim 1, wherein the critical passive components comprise at least one capacitor and at least one microelectromechanical system (MEMS).

4. A method according to claim 1 wherein the critical passive components comprise at least one capacitor or at least one microelectromechanical system (MEMS).

5. A method according to claim 3, wherein a dielectric material of the at least one capacitor comprises a perovskite.

6. A method according to claim 1, wherein producing the second substrate comprises producing an electrically conductive material.

7. A method according to claim 1, wherein producing the second substrate comprises producing a dielectric material.

8. A method according to claim 7, wherein producing the second substrate comprises producing perovskite.

9. A method according to claim 1 further comprising producing dielectric insulation trenches in the second substrate during the production of the second substrate.

10. A method according to claim 1 further comprising producing at least one non-critical passive component during the production of the second substrate.

11. A method according to claim 10, wherein producing the non-critical passive component comprises producing a capacitor in trenches.

12. A method according to claim 9 further comprising producing at least one inductor in the vicinity of a face of the second substrate opposite a bonding face after the bonding of the two substrates.

13. A method according to claim 12 further comprising producing the at least one inductor on the dielectric insulation trenches.

14. A die fabricated by a method according to claim 1.

25. A method according to claim 13, wherein the at least one inductor and at least one of the interconnection lines are produced during a same process step.

26. The method according to claim 1, wherein the first temperature is about 450°

C.

27. The method according to claim 1, wherein producing the first substrate comprises producing a substrate including all of the active components of the integrated circuit, and wherein producing the second substrate comprises producing a substrate including only passive components.

28. The method according to claim 1, wherein producing the first substrate further comprises producing the at least one active component comprising an interconnect metal that unacceptably degraded at a temperature above the first temperature.

15. A die made of a single stack of layers, containing an integrated circuit comprising active components produced at a temperature lower than a first temperature above which the active components are unacceptably degraded and comprising passive components,

wherein at least a part of the passive components comprising critical passive components produced at a temperature higher than the first temperature above which the active components are unacceptably degraded,

wherein the die comprises an interface between two of the layers such that a first portion of the die situated on one side of the interface includes the active component and a second portion of the die situated on the other side of the interface includes the critical passive components produced at the temperature higher than the first temperature,

wherein the die comprises at least one interconnection line between the components of the first and second portions, the interconnection line passing through the second portion of the die.

16. A die according to claim 15 wherein the critical passive components comprise at least one capacitor and at least one MEMS enclosed in a cavity situated inside the die.

17. A die according to claim 16, wherein the at least one capacitor comprises a dielectric material comprising perovskite.

18. A die according to claim 15, wherein the die further comprises dielectric insulation trenches.

19. A die according to claim 15, wherein the integrated circuit further comprises at least one non-critical passive component.

20. A die according to claim 19 wherein the non-critical passive component comprises a capacitor in trenches.

21. A die according to claim 15, wherein the active components are disposed in the vicinity of a first face of the die and wherein the integrated circuit further comprises at least one inductor situated in a vicinity of the face of the die opposite the first face.

22. A die according to claim 21, wherein the at least one inductor is situated on inductive insulation trenches.

23. A die according to any one of claim 15, wherein the active components are disposed in a vicinity of a first face of the die and the die further comprises at least one interconnection line that emerges in the vicinity of the face of the die opposite the first face.

24. A die according to any one of claim 19 wherein the active components are disposed in a vicinity of a first face of the die and the die further comprises at least one interconnection line that emerges in the vicinity of the face of the die opposite the first face.