Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material

• US 8,048,811 B2
• Filed: 01/16/2009
• Issued: 11/01/2011
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Feustel, Frank, Werner, Thomas, Boemmels, Juergen
• Primary Examiner(s): Maldonado, Julio J
• Application Number:
  US12/354,884
• Publication Number:
  US 20090246951A1
• Time in Patent Office: 1,019 Days
• Field of Search: 438/624, 438/637, 438/638, 438/700, 438/717, 438/738, 438/625, 438/639, 438/694, 438/734, 438/736, 257/E21.257, 257/E21.576, 257/E21.579, 257/E21.577, 216/47, 216/51, 216/72, 216/74
• US Class Current: 438/717
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric

Abstract

By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree of etch selectivity during the patterning of openings in a metallization layer of a semiconductor device.

Claims

1. A method, comprising:

forming a stack of layers on a low-k dielectric layer formed above a substrate of a semiconductor device, said stack of layers comprising a hardmask layer formed above said low-k dielectric layer and a first cap layer formed on said hardmask layer;

forming a first opening in said stack of layers corresponding to a via opening to be formed in said low-k dielectric layer;

forming a first portion of said via opening in said low-k dielectric layer after forming said first opening using said hardmask layer as a first etch mask;

forming a trench etch mask by forming a second opening in said hardmask layer after forming said first portion of said via opening; and

performing an etching process to form a second portion of said via opening and to form a trench in said low-k dielectric layer on the basis of said trench etch mask, wherein said cap layer is removed from above said hardmask layer during said etching process.

2. The method of claim 1, further comprising forming a second cap layer in said first opening prior to forming said second opening.

3. The method of claim 1, further comprising etching through an etch stop layer formed below said low-k dielectric layer to form said via opening to extend to a contact region formed below said etch stop layer.

4. The method of claim 1, further comprising filling said via opening and said trench with a metal in a common fill process.

5. The method of claim 4, further comprising forming a conductive barrier layer in said trench and said via opening prior to filling said via opening and said trench with a metal.

6. The method of claim 5, further comprising removing excess material and at least a portion of said hardmask layer by a planarization process.

7. The method of claim 1, wherein forming said stack of layers comprises forming a bottom cap layer above said low-k dielectric layer and forming said hardmask layer on said bottom cap layer.

8. The method of claim 7, further comprising removing said hardmask layer after forming said trench by using said bottom cap layer as a stop material.

9. The method of claim 1, wherein said hardmask layer comprises a metal.

10. The method of claim 9, wherein said metal is at least one of tantalum and titanium.

11. The method of claim 1, wherein said first cap layer is comprised of at least one of silicon dioxide and carbon.

12. A method, comprising:

forming a hardmask layer above a dielectric material of a metallization layer of a semiconductor device, said hardmask layer comprising a first material layer formed above said dielectric material and a second material layer formed on said first material layer;

forming a first opening in said hardmask layer, said first opening corresponding to a via opening to be formed in said dielectric material;

forming a cap layer above said hardmask layer and in said first opening;

after forming said cap layer, forming said via opening in said dielectric material after forming said first opening using at least said first material layer of said hardmask layer as an etch mask;

forming a second opening in said hardmask layer after forming said via opening, said second opening corresponding to a trench to be formed in said dielectric material; and

performing an etching process to form said trench in said dielectric material by using said first material layer as an etch mask, wherein said cap layer and said second material layer are removed from above said first material layer during said etching process.

13. The method of claim 12, further comprising removing said first material layer by chemical mechanical polishing.

14. The method of claim 13, further comprising filling said via opening and said trench with a metal-containing material and removing said hardmask layer after removing excess material of said metal-containing material.

15. The method of claim 13, wherein said first material layer of said hardmask layer comprises a metal.

16. The method of claim 12, further comprising forming a bottom layer above said dielectric material prior to forming said hardmask layer.

17. The method of claim 12, wherein forming said second opening in said hardmask layer comprises forming a patterned resist layer above said hardmask layer, performing an etching process to form said second opening, and removing said patterned resist layer prior to forming said trench.

18. The method of claim 12, wherein said cap layer is formed after forming said via opening and wherein said method further comprises forming a planarization material in said via opening prior to forming said second opening.

19. The method of claim 12, wherein forming said via opening comprises forming a first portion of said second opening in said second material layer and forming a first portion of said via opening in said dielectric layer prior to forming a second portion of said second opening in said first material layer.

20. The method of claim 19, further comprising forming a second portion of said via opening and said trench in a common etch sequence.

21. A method of patterning a dielectric material of a metallization layer of a semiconductor device, the method comprising:

forming a first hardmask layer above said dielectric material;

forming a second hardmask layer on said first hardmask layer;

forming a first opening in said first and second hardmask layers, said first opening corresponding to a via opening to be formed in said dielectric material;

forming a second opening in said second hardmask layer and a first portion of said via opening in said dielectric material after forming said first opening, said second opening corresponding to a trench to be formed in said dielectric material;

forming said second opening in said first hardmask layer; and

performing an etching process to form said trench and to form a second portion of said via opening by using said first hardmask layer as an etch mask, wherein said second hardmask layer is removed from above said first hardmask layer during said etching process.

22. The method of claim 21, further comprising forming a cap layer in said first opening prior to forming said second opening.

23. The method of claim 22, further comprising removing said first hardmask layer after forming said second portion of the via opening and said trench.

24. The method of claim 23, wherein said first hardmask layer comprises a metal.