Semiconductor device having variable parameter selection based on temperature and test method

• US 8,049,145 B1
• Filed: 02/20/2007
• Issued: 11/01/2011
• Est. Priority Date: 04/19/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Agersonn RALL Group LLC (Intellectual Ventures LLC)
• Inventors: Walker, Darryl
• Primary Examiner(s): PASCHALL, MARK H
• Application Number:
  US11/708,174
• Time in Patent Office: 1,715 Days
• Field of Search: 219/501, 219/502, 219483-487, 219/497, 219/499, 219/505, 219/209, 219/210, 365/211, 365/221, 365/222, 365/189, 365/5, 365/189.08, 365/189.09, 365/212
• US Class Current: 219/502
• CPC Class Codes: G01K 7/425 Thermal management of integrated systems

Abstract

A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Claims

1. A semiconductor memory device, comprising:

a temperature-sensing circuit including;

a first amplifier comprising a first positive input and a first negative input, wherein the first negative input is configured to be driven by a temperature-independent signal;

a first transistor electrically connected to the first positive input, wherein the first transistor is configured to be controlled by a temperature signal; and

a first temperature threshold resistance and a first hysteresis resistance both electrically connected in series to the first positive input, wherein the first hysteresis resistance is configured to be controlled, at least in part, by an output of the first amplifier; and

a word line driving circuit configured to provide a first word line disable voltage based on the output of the first amplifier.

2. The semiconductor memory device of claim 1, wherein the first word line disable voltage is a negative voltage with respect to a ground voltage.

3. The semiconductor memory device of claim 1, wherein the temperature threshold resistance is configured to be programmable.

4. The semiconductor memory device of claim 1, wherein the first temperature threshold resistance comprises a first temperature threshold value and the first hysteresis resistance comprises a first temperature hysteresis value.

5. The semiconductor memory device of claim 1, wherein the hysteresis resistance is configured to be programmable.

6. The semiconductor memory device of claim 1, further comprising:

a second temperature-sensing circuit including;

a second amplifier including a second positive input and a second negative input, wherein the second negative input is configured to be driven by the temperature-independent signal;

a second transistor electrically connected to the second positive input, wherein the second transistor is configured to be controlled by the temperature signal; and

a second temperature threshold resistance and a second hysteresis resistance both electrically connected in series to the second positive input, wherein the second hysteresis resistance is configured to be controlled, at least in part, by an output of the second amplifier;

wherein the word line driving circuit is further configured to provide a second word line disable voltage based on the output of the second amplifier.

7. The semiconductor memory device of claim 6, wherein the second word line disable voltage is less than the first word line disable voltage.

8. The semiconductor memory device of claim 1, wherein the word line driving circuit further comprises a negative voltage generator configured to generate the first word line disable voltage.

9. The semiconductor memory device of claim 1, further comprising a band gap reference circuit configured to provide the temperature-independent signal.

10. The semiconductor memory device of claim 1, wherein the output of the first amplifier comprises a temperature indication signal.

11. An apparatus comprising:

a temperature-sensing circuit including;

an amplifier comprising a positive input, a negative input, and an output, wherein the first negative input is configured to be driven by a temperature-independent signal, and wherein the output is associated with a binary temperature indication;

a transistor electrically connected to the first positive input, wherein the transistor is configured to be controlled by a temperature signal; and

a temperature threshold resistance associated with a temperature threshold value and a hysteresis resistance associated with a hysteresis value, wherein the temperature threshold resistance and the hysteresis resistance are both electrically connected in series to the first positive input, and wherein the hysteresis resistance is configured to be controlled, at least in part, by an output of the amplifier; and

a word line driving circuit configured to provide a word line disable voltage based on the binary temperature indication.

12. The apparatus of claim 11, wherein the word line driving circuit is configured to drive at least one of a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a random access memory (RAM) device.

13. The apparatus of claim 11, wherein the temperature threshold resistance and the hysteresis resistance are both configured to be programmable.