Thin film transistor, method of fabricating a thin film transistor and flat panel display device having the same

• US 8,049,212 B2
• Filed: 12/23/2008
• Issued: 11/01/2011
• Est. Priority Date: 12/24/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Mo, Yeon-Gon, Jeong, Jae-Kyeong, Jeong, Jong-Han, Shin, Hyun-Soo
• Primary Examiner(s): Mandala; Victor A
• Application Number:
  US12/318,212
• Publication Number:
  US 20090159879A1
• Time in Patent Office: 1,043 Days
• Field of Search: 257/43, 257/E33.014, 257/E21.411, 438/104
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A TFT includes a substrate, a transparent semiconductor layer on the substrate, the transparent semiconductor layer including zinc oxide and exhibiting a surface roughness of about 1.3 nm or less, a gate electrode on the transparent semiconductor layer, a gate insulating layer between the gate electrode and the transparent semiconductor layer, the gate insulting layer insulating the gate electrode from the transparent semiconductor layer, and source and drain electrodes on the substrate, the source and drain electrodes being in contact with the transparent semiconductor layer.

Claims

1. A thin film transistor (TFT), comprising:

a substrate;

a transparent semiconductor layer on the substrate, the transparent semiconductor layer including zinc oxide and being a patterned atomic deposition layer with a surface roughness of about 1.3 nm or less;

a gate electrode on the transparent semiconductor layer;

a gate insulating layer between the gate electrode and the transparent semiconductor layer, the gate insulting layer insulating the gate electrode from the transparent semiconductor layer; and

source and drain electrodes on the substrate, the source and drain electrodes being in contact with the transparent semiconductor layer.

2. The TFT as claimed in claim 1, wherein the substrate includes one or more of a single crystalline silicon, glass, plastic, sapphire and quartz.

3. The TFT as claimed in claim 1, wherein the transparent semiconductor layer has a thickness of about 30 nm to about 150 nm.

4. The TFT as claimed in claim 1, further comprising:

a buffer layer between the substrate and the transparent semiconductor layer; and

an interlayer insulating layer on the gate electrode, the source and drain electrodes being on the interlayer insulating layer.

5. A method of fabricating a thin film transistor (TFT), comprising:

forming a transparent semiconductor layer on a substrate, the transparent semiconductor layer including zinc oxide and exhibiting a surface roughness of about 1.3 nm or less, wherein forming the transparent semiconductor layer includes;

forming a zinc oxide layer on the substrate by atomic layer deposition; and

patterning the zinc oxide layer to form the transparent semiconductor layer,

forming a gate insulating layer on the transparent semiconductor layer;

forming a gate electrode on the gate insulting layer, the gate insulting layer insulating the gate electrode from the transparent semiconductor layer; and

forming source and drain electrodes on the substrate and in contact with the transparent semiconductor layer.

6. The method as claimed in claim 5, further comprising:

forming a buffer layer between the substrate and the transparent semiconductor layer; and

forming an interlayer insulating layer on the gate electrode, the source and drain electrodes being formed on the interlayer insulating layer.

7. The method as claimed in claim 5, wherein the atomic layer deposition includes using water vapor (H₂O) and/or ozone (O₃) as oxidizing agents.

8. The method as claimed in claim 5, wherein forming the transparent semiconductor layer includes forming the transparent semiconductor layer to a thickness of about 30 nm to about 150 nm.

9. The method as claimed in claim 5, wherein the substrate is formed of one or more of a single crystalline silicon, glass, plastic, sapphire and quartz.

10. A flat panel display (FPD) device, comprising:

a thin film transistor (TFT), including;

a transparent semiconductor layer on a substrate, the transparent semiconductor layer including zinc oxide and being a patterned atomic deposition layer with a surface roughness of about 1.3 nm or less,

a gate electrode on the transparent semiconductor layer,

a gate insulating layer between the gate electrode and the transparent semiconductor layer, the gate insulting layer insulating the gate electrode from the transparent semiconductor layer, and

source and drain electrodes on the substrate, the source and drain electrodes being in contact with the transparent semiconductor layer; and

a pixel part including at least one pixel and being in electrical communication with the TFT via at least one of the source and drain electrodes of the TFT.

11. The FPD device as claimed in claim 10, wherein the substrate of the TFT includes one or more of a single crystalline silicon, glass, plastic, sapphire and quartz.

12. The FPD device as claimed in claim 10, wherein the transparent semiconductor layer of the TFT has a thickness of about 30 nm to about 150 nm.

13. The FPD device as claimed in claim 10, wherein the FPD is an organic light emitting diode (OLED) display device.

14. The FPD device as claimed in claim 13, wherein the pixel part is connected to the source and drain electrodes of the TFT via at least one electrode layer of an OLED.

15. The FPD device as claimed in claim 10, further comprising:

a buffer layer between the substrate and the transparent semiconductor layer; and

an interlayer insulating layer on the gate electrode, the source and drain electrodes being on the interlayer insulating layer.