Semiconductor device and method for manufacturing the same

• US 8,049,225 B2
• Filed: 08/05/2009
• Issued: 11/01/2011
• Est. Priority Date: 08/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Shiraishi, Kojiro, Miyairi, Hidekazu, Yamazaki, Shunpei, Akimoto, Kengo, Miyanaga, Akiharu
• Primary Examiner(s): Mandala; Victor A
• Application Number:
  US12/535,711
• Publication Number:
  US 20100032665A1
• Time in Patent Office: 818 Days
• Field of Search: 257/78, 257/43, 257/614, 257/E29.296
• US Class Current: 257/78
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Claims

1. A semiconductor device comprising:

a thin film transistor, the thin film transistor comprising;

a source electrode layer and a drain electrode layer;

a buffer layer having n-type conductivity over the source electrode layer and the drain electrode layer;

a semiconductor layer over the buffer layer;

a gate insulating layer over the semiconductor layer; and

a gate electrode layer over the gate insulating layer,

wherein the semiconductor layer and the buffer layer are oxide semiconductor layers,

wherein a carrier concentration of the buffer layer is higher than a carrier concentration of the semiconductor layer, and

wherein each of the source electrode layer and the drain electrode layer is electrically connected to the semiconductor layer with the buffer layer interposed between the source electrode layer or the drain electrode layer and the semiconductor layer.

2. The semiconductor device according to claim 1, wherein each one edge of the source electrode layer and the drain electrode layer is covered with the buffer layer.

3. The semiconductor device according to claim 1, wherein the buffer layer contains an impurity element imparting n-type conductivity.

4. The semiconductor device according to claim 1, wherein the carrier concentration of the semiconductor layer is lower than 1×

10¹⁷ atoms/cm³, and the carrier concentration of the buffer layer is 1×

10¹⁸ atoms/cm³ or higher.

5. The semiconductor device according to claim 1, further comprising a second buffer layer between the semiconductor layer and the buffer layer, wherein a carrier concentration of the second buffer layer is higher than the carrier concentration of the semiconductor layer and lower than the carrier concentration of the buffer layer.

6. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer contain titanium.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layers contain indium, gallium, and zinc.

8. A semiconductor device comprising:

a thin film transistor, the thin film transistor comprising;

a source electrode layer and a drain electrode layer;

a buffer layer having n-type conductivity over the source electrode layer and the drain electrode layer;

a semiconductor layer over the buffer layer;

a gate insulating layer over the semiconductor layer; and

a gate electrode layer over the gate insulating layer,

wherein the semiconductor layer and the buffer layer are oxide semiconductor layers,

wherein the gate electrode layer does not overlap with the source electrode layer and the drain electrode layer at a channel formation region of the semiconductor layer interposed between the source electrode layer and the drain electrode layer,

wherein a carrier concentration of the buffer layer is higher than a carrier concentration of the semiconductor layer, and

wherein each of the source electrode layer and the drain electrode layer is electrically connected to the semiconductor layer with the buffer layer interposed between the source electrode layer or the drain electrode layer and the semiconductor layer.

9. The semiconductor device according to claim 8, wherein each one edge of the source electrode layer and the drain electrode layer is covered with the buffer layer.

10. The semiconductor device according to claim 8, wherein the buffer layer contains an impurity element imparting n-type conductivity.

11. The semiconductor device according to claim 8, wherein the carrier concentration of the semiconductor layer is lower than 1×

10¹⁷ atoms/cm³, and the carrier concentration of the buffer layer is 1×

10¹⁸ atoms/cm³ or higher.

12. The semiconductor device according to claim 8, further comprising a second buffer layer between the semiconductor layer and the buffer layer, wherein a carrier concentration of the second buffer layer is higher than the carrier concentration of the semiconductor layer and lower than the carrier concentration of the buffer layer.

13. The semiconductor device according to claim 8, wherein the source electrode layer and the drain electrode layer contain titanium.

14. The semiconductor device according to claim 8, wherein the oxide semiconductor layers contain indium, gallium, and zinc.