Semiconductor device including memory cell having charge accumulation layer

• US 8,049,259 B2
• Filed: 12/13/2010
• Issued: 11/01/2011
• Est. Priority Date: 12/07/2007
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Noguchi, Mitsuhiro, Gomikawa, Kenji
• Primary Examiner(s): Luu; Chuong A.
• Application Number:
  US12/966,115
• Publication Number:
  US 20110079835A1
• Time in Patent Office: 323 Days
• Field of Search: 257/295, 257/296, 257/298, 257/254, 257/300, 257/324, 257/532, 257/306, 257/303, 257/311, 257/344
• US Class Current: 257/296
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

Claims

1. A semiconductor device comprising:

element regions each of which is surrounded by an element isolation region, the element regions having transistor regions and capacitor regions;

MOS transistors each of which is formed on one of the transistor regions, each of the MOS transistors having a source, a drain, and a gate;

capacitor elements each of which is formed on one of the capacitor regions;

a voltage generating circuit in which current paths of the MOS transistors are series-connected and each of the capacitor elements is connected to one of the MOS transistors via either of the source and the drain thereof, the voltage generating circuit outputting a voltage from a first MOS transistor in a final stage of the series connection, the voltage generating circuit inputting a voltage from a second MOS transistor in a previous stage in the series connection;

a first impurity-doped region which is formed on at least either of the source and the drain;

a contact plug which is formed on the first impurity-doped region to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements, a distance between the gate and the first impurity-doped region for the first MOS transistor being larger than that for the second MOS transistor; and

a memory cell which is capable of holding data, the voltage output by the voltage generating circuit being applied to the memory cell.

2. The device according to claim 1, wherein each of the capacitor elements includes:

a n-type well region which is formed in a surface region of the one of the capacitor regions and acts as one of electrodes;

an insulation film which is formed on the well region; and

a gate which is formed on the insulation film and acts as the other electrode.

3. The device according to claim 1, wherein the one of the transistor regions contains a p-type impurity which is doped with a concentration of 10¹⁴ cm⁻

3 to 5×

10¹⁶ cm<sup>−

3</sup> in a region from a surface to a depth of 1 μ

m.

4. The device according to claim 1, further comprising a second impurity-doped region which is provided immediately below the element isolation region and has a peak concentration of a p-type impurity of 10¹⁶ cm⁻

3 to 10¹⁸ cm<sup>−

3</sup>,

wherein an interval between one of the element regions and the second impurity-doped region ranges from 0.2 μ

m to 1.6 μ

m.

5. The device according to claim 1, wherein a first clock signal is input to one end of the current path of one of the MOS transistors in an even-numbered stage through one of the capacitor elements, and

a second clock signal is input to one end of the current path of one of the MOS transistors in an odd-numbered stage through one of the capacitor elements, the second clock signal differing from the first clock signal in phase.

6. The device according to claim 1, wherein each of the MOS transistors includes:

a first gate electrode layer which is formed on the first one of the element regions with a first gate insulation film interposed therebetween; and

a second gate electrode layer which is formed on the first gate electrode layer with a first inter-gate insulation film interposed therebetween, the second gate electrode layer being electrically connected to the first gate electrode layer, and

the memory cell includes;

a charge accumulation layer which is formed on a semiconductor substrate with a second gate insulation film interposed therebetween; and

a control gate electrode which is formed on the charge accumulation layer with a second inter-gate insulation film interposed therebetween, the control gate electrode being electrically isolated to the charge accumulation layer.

7. The device according to claim 1, wherein an impurity concentration of the first impurity-doped region is higher than that of the source and the drain.

8. The device according to claim 1, wherein the first impurity-doped region is formed deeper than the source and the drain.

9. The device according to claim 1, wherein the distance between the gate and the first impurity-doped region in a latter stage of the series-connection of the MOS transistors is equal to or greater than that in a former stage of the MOS transistor.

10. A semiconductor device comprising:

element regions each of which is surrounded by an element isolation region, the element regions having transistor regions and capacitor regions;

MOS transistors each of which is formed on one of the transistor regions, each of the MOS transistors having a source, a drain, and a gate;

capacitor elements each of which is formed on one of the capacitor regions;

a voltage generating circuit in which current paths of the MOS transistors are series-connected and each of the capacitor elements is connected to one of the MOS transistors via either of the source and the drain thereof, the voltage generating circuit outputting a voltage from a first MOS transistor in a final stage of the series connection, the voltage generating circuit inputting a voltage from a second MOS transistor in a previous stage in the series connection;

a first impurity-doped region which is formed on at least either of the source and the drain;

a contact plug which is formed on the first impurity-doped region to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements, a distance between the gate and the first impurity-doped region for the first MOS transistor being larger than that for the second MOS transistor, a distance in a gate width direction of the gate between the contact plug for the first MOS transistor and the element isolation region being larger than that between the contact plug for the second MOS transistor and the element isolation region; and

a memory cell which is capable of holding data, the voltage output by the voltage generating circuit being applied to the memory cell.

11. The device according to claim 10, wherein each of the capacitor elements includes:

a n-type well region which is formed in a surface region of the one of the capacitor regions and acts as one of electrodes;

an insulation film which is formed on the well region; and

a gate which is formed on the insulation film and acts as the other electrode.

12. The device according to claim 10, wherein the one of the transistor regions contains a p-type impurity which is doped with a concentration of 10¹⁴ cm⁻

3 to 5×

10¹⁶ cm<sup>−

3</sup> in a region from a surface to a depth of 1 μ

m.

13. The device according to claim 10, further comprising a second impurity-doped region which is provided immediately below the element isolation region and has a peak concentration of a p-type impurity of 10¹⁶ cm⁻

3 to 10¹⁸ cm<sup>−

3</sup>,

wherein an interval between one of the element regions and the second impurity-doped region ranges from 0.2 μ

m to 1.6 μ

m.

14. The device according to claim 10, wherein a first clock signal is input to one end of the current path of one of the MOS transistors in an even-numbered stage through one of the capacitor elements, and

a second clock signal is input to one end of the current path of one of the MOS transistors in an odd-numbered stage through one of the capacitor elements, the second clock signal differing from the first clock signal in phase.

15. The device according to claim 10, wherein each of the MOS transistors includes:

a first gate electrode layer which is formed on the one of the transistor regions with a first gate insulation film interposed therebetween; and

a second gate electrode layer which is formed on the first gate electrode layer with a first inter-gate insulation film interposed therebetween, the second gate electrode layer being electrically connected to the first gate electrode layer, and

the memory cell includes;

a charge accumulation layer which is formed on a semiconductor substrate with a second gate insulation film interposed therebetween; and

a control gate electrode which is formed on the charge accumulation layer with a second inter-gate insulation film interposed therebetween, the control gate electrode being electrically isolated to the charge accumulation layer.

16. The device according to claim 10, wherein an impurity concentration of the first impurity-doped region is higher than that of the source and the drain.

17. The device according to claim 10, wherein the first impurity-doped region is formed deeper than the source and the drain.

18. The device according to claim 10, wherein the distance between the gate and the first impurity-doped region in a latter stage of the series-connection of the MOS transistors is equal to or greater than that in a former stage of the series-connection of the MOS transistors,

the distance in a gate width direction between the contact plug and the element isolation region in a latter stage of the series-connection of the MOS transistors is equal to or greater than that in a former stage of the series-connection of the MOS transistors.

19. A semiconductor device comprising:

element regions each of which is surrounded by an element isolation region, the element regions having transistor regions and capacitor regions;

MOS transistors each of which is formed on one of the transistor regions, each of the MOS transistors having a source, a drain, and a gate;

capacitor elements each of which is formed on one of the capacitor regions;

a voltage generating circuit in which current paths of the MOS transistors are series-connected and each of the capacitor elements is connected to one of the MOS transistors via either of the source and the drain thereof, the voltage generating circuit outputting a voltage from a first MOS transistor in a final stage of the series connection, the voltage generating circuit inputting a voltage from a second MOS transistor in a previous stage in the series connection;

a first impurity-doped region which is formed on at least either of the source and the drain;

a second impurity-doped region which is formed immediately below the element isolation region and surrounds the element regions; and

a contact plug which is formed on the first impurity-doped region to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements, a distance between the gate and the first impurity-doped region for the first MOS transistor being larger than that for the second MOS transistor, a distance between one of the transistor regions for the first MOS transistor and the second impurity-doped region being larger than that between one of the transistor regions for the second MOS transistor and the second impurity-doped region; and

a memory cell which is capable of holding data, the voltage output by the voltage generating circuit being applied to the memory cell.

20. The device according to claim 19, wherein each of the capacitor elements includes:

a n-type well region which is formed in a surface region of the one of the capacitor regions and acts as one of electrodes;

an insulation film which is formed on the well region; and

a gate which is formed on the insulation film and acts as the other electrode.

21. The device according to claim 19, wherein the one of the transistor regions contains a p-type impurity which is doped with a concentration of 10¹⁴ cm⁻

3 to 5×

10¹⁶ cm<sup>−

3</sup> in a region from a surface to a depth of 1 μ

m.

22. The device according to claim 19, wherein the second impurity-doped region contains p-type impurity,

the p-type impurity has a peak concentration of 10¹⁶ cm⁻

3 to 10¹⁸ cm<sup>−

3</sup>, and

an interval between one of the element regions and the second impurity-doped region ranges from 0.2 μ

m to 1.6 μ

m.

23. The device according to claim 19, wherein a first clock signal is input to one end of the current path of one of the MOS transistors in an even-numbered stage through one of the capacitor elements, and

a second clock signal is input to one end of the current path of one of the MOS transistors in an odd-numbered stage through one of the capacitor elements, the second clock signal differing from the first clock signal in phase.

24. The device according to claim 19, wherein an impurity concentration of the first impurity-doped region is higher than that of the source and the drain.

25. The device according to claim 19, wherein the first impurity-doped region is formed deeper than the source and the drain.

26. The device according to claim 19, wherein the distance between the gate and the first impurity-doped region in a latter stage of the series-connection of the MOS transistors is equal to or greater than that in a former stage of the series-connection of the MOS transistors,

the distance between the one of the transistor regions and the second impurity-doped region in a latter stage of the series-connection of the MOS transistors is equal to or greater than that in a former stage of the series-connection of the MOS transistors.