Power semiconductor device having a voltage sustaining layer with a terraced trench formation of floating islands

• US 8,049,271 B2
• Filed: 05/03/2010
• Issued: 11/01/2011
• Est. Priority Date: 10/04/2001
• Status: Expired due to Fees

• Current Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Inventors: Guillot, Jean-Michel, Blanchard, Richard A.
• Primary Examiner(s): Mai; Anh
• Application Number:
  US12/772,258
• Publication Number:
  US 20100207198A1
• Time in Patent Office: 547 Days
• Field of Search: 257/327, 257/328, 257/339, 257/342, 257/E29.257
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region. A filler material is deposited in the terraced trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

Claims

1. A power semiconductor device comprising:

a substrate of a second conductivity type;

a voltage sustaining region disposed on said substrate, said voltage sustaining region including;

an epitaxial layer having a first conductivity type;

at least one terraced trench located in said epitaxial layer, said terraced trench having a plurality of sidewalls, and a plurality of portions that differ in width to define at least one annular ledge therebetween;

at least one annular doped region having a dopant of a second conductivity type, said annular doped region being located in said epitaxial layer below and adjacent to said annular ledge, wherein said plurality of sidewalls do not have dopant implanted therein;

a filler material substantially filling said terraced trench; and

at least one active region of said second conductivity disposed over said voltage sustaining region to define a junction therebetween.

2. The device of claim 1 wherein said plurality of portions of the terraced trench includes a smallest width portion and a largest width portion, said smallest width portion being located at a depth in said epitaxial layer such that it is closer to the substrate than a largest width portion.

3. The device of claim 1 wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions.

4. The device of claim 1 wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions.

5. The device of claim 1 wherein said epitaxial layer has a given thickness and a first portion of the terraced trench is etched into said epitaxial layer by an amount substantially equal to 1/(x+1) of said given thickness, where x is equal to or greater than a prescribed number of annular doped regions to be formed in the voltage sustaining region.

6. The device of claim 1 wherein said material filling the trench is a dielectric material.

7. The device of claim 6 wherein said dielectric material is silicon dioxide.

8. The device of claim 7 wherein said dielectric material is silicon nitride.

9. The device of claim 1 wherein said dopant is boron.

10. The device of claim 4 wherein a surface area of the at least two annular ledges are substantially equal to one another.

11. The device of claim 1 wherein said at least one active region further includes:

a gate dielectric and a gate conductor disposed above said gate dielectric;

first and second body regions located in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type; and

first and second source regions of the first conductivity type located in the first and second body regions, respectively.

12. The device of claim 1 wherein said terraced trench has a circular cross-section.

13. The device of claim 1 wherein said terraced trench has a cross-sectional shape selected from the group consisting of a square, rectangle, octagon, and a hexagon.

14. A power semiconductor device made in accordance with the method comprising the steps of:

A. providing a substrate of a second conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

2. forming at least one terraced trench in said epitaxial layer, said terraced trench having a plurality of portions that differ in width to define at least one annular ledge therebetween;

3. depositing a barrier material along the walls and bottom of said trench;

4. implanting a dopant of a second conductivity type through the barrier material lining said at least one annular ledge and said trench bottom and into adjacent portions of the epitaxial layer, wherein dopant is not implanted into the walls of said trench;

5. diffusing said dopant to form at least one annular doped region in said epitaxial layer and at least one other region located below said annular doped region in said epitaxial layer;

6. depositing a filler material in said terraced trench to substantially fill said terraced trench; and

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween, wherein step (C) further includes the steps of;

forming an insulated gate electrode comprising oxide and polysilicon layers;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type; and

forming first and second source regions of the first conductivity type in the first and second body regions, respectively,

wherein said body regions include regions that extend deeper than a depth of said first and second source regions.

15. A power semiconductor device according to claim 14, wherein

said plurality of portions of the terraced trench:

are coaxially located with respect to one another;

includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions; and

wherein the step of forming at least one terraced trench includes the steps of successively etching said at least three portions of the terraced trench beginning with a largest width portion and ending with a smallest width portion.

16. A power semiconductor device according to claim 14, wherein step (C) further includes the steps of:

forming a gate conductor above a gate dielectric region;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively.