Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices

• US 8,049,307 B2
• Filed: 01/23/2009
• Issued: 11/01/2011
• Est. Priority Date: 01/23/2009
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Wu, Chen-Wei, Chang, Jui-Chun, Jou, Yeh-Ning, Tu, Shang-Hui
• Primary Examiner(s): Stark; Jarrett
• Application Number:
  US12/358,943
• Publication Number:
  US 20100187566A1
• Time in Patent Office: 1,012 Days
• Field of Search: 257/517, 257/525, 257/556, 257/557, 257/575, 257/E51.004
• US Class Current: 257/556
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Abstract

Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P⁺ doped drain region is disposed in the high-V N-well. A P⁺ diffused region and an N⁺ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N⁺ doped source region and the other end extending over the insulation region.

Claims

1. An insulated gate bipolar transistor electrostatic discharge (IGBT-ESD) protection device, comprising:

a P-type semiconductor substrate;

a patterned insulation region disposed on the P-type semiconductor substrate defining a first active region and a second active region;

a high-voltage N-well formed in the first active region of the P-type semiconductor substrate;

a P-body doped region formed in the second active region of the P-type semiconductor substrate, wherein the high-voltage N-well and the P-body doped region are separated with a predetermined distance exposing the P-type semiconductor substrate;

a P⁺ doped drain region disposed in the high-voltage N-well;

a P⁺ diffused region and an N⁺ doped source region disposed in the P-body doped region;

a gate structure disposed on the P-type semiconductor substrate with one end adjacent to the N⁺ doped source region and with the other end extending over the patterned insulation region; and

a diffusion region extending from the high-voltage N-well to the P-body doped region, wherein the diffusion region and the P-body doped region are separated from each other only by a portion of the P-type semiconductor substrate free from any additionally doped region, and wherein a bottom of the diffusion region is aligned with that of the high-voltage N-well.

2. The IGBT-ESD protection device as claimed in claim 1, wherein the area of the P⁺ doped drain region is smaller than the area of the first active region.

3. The IGBT-ESD protection device as claimed in claim 2, wherein the P⁺ doped drain region comprises a plurality of separated islands.

4. The IGBT-ESD protection device as claimed in claim 1, wherein the P-type semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.

5. The IGBT-ESD protection device as claimed in claim 1, wherein the portion of the P-type semiconductor substrate has a first boundary to the diffusion region and a second boundary to the P-body doped region, wherein the first and second boundaries are both directly under the gate structure and laterally between the second active region and the patterned insulation region.