Device for avoiding parasitic capacitance in an integrated circuit package

• US 8,049,340 B2
• Filed: 03/22/2006
• Issued: 11/01/2011
• Est. Priority Date: 03/22/2006
• Status: Active Grant
• 

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Hall, Jeffrey, Amin, Amar, Jenkins, Michael, Nikoukary, Shawn
• Primary Examiner(s): Fahmy; Wael
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US11/277,188
• Publication Number:
  US 20070222084A1
• Time in Patent Office: 2,050 Days
• Field of Search: 257/792, 257/777, 257/700, 257/798, 257/728, 257/E23.019, 257/E23.151, 257/E23.152, 257/E23.153, 257/E23.175, 257/758, 257/693, 257/698, 257/760, 257/691, 257/692, 257/E23.062, 257/778
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0224 Patterned shielding planes, ground planes or power planes H05K1/0253 takes precedence
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out

Abstract

An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

Claims

1. An integrated circuit package substrate comprising:

a first and a second electrically conductive layer separated from each other by an electrically insulating layer with no intermediate conductive layer therebetween;

a plurality of rows of contact pads formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board; and

a plurality of cutouts formed in the second electrically conductive layer for reducing parasitic capacitance between the second electrically conductive layer and the first electrically conductive layer, wherein each cutout encloses an electrically insulating area within the second electrically conductive layer, and wherein each electrically insulating area completely overlaps a corresponding one of the contact pads formed in the first electrically conductive layer such that there is substantially no overlap of the rows of contact pads with metal in the second electrically conductive layer.

2. The integrated circuit package substrate of claim 1 further comprising transmit and receive rows of ball pads as the contact pads operable with the second electrically conductive layer for converting a serial data stream to or from a parallel data stream, the second electrically conductive layer being a routing layer including routing traces, the cutouts being arranged in rows corresponding to the rows of ball pads.

3. The integrated circuit package substrate of claim 1 wherein the cutouts have the same dimensions as the contact pads.

4. The integrated circuit package substrate of claim 1, further comprising a third electrically conductive layer separated from the second electrically conductive layer by a second electrically insulating layer, the third electrically conductive layer including a plurality of cutouts each of which encloses an electrically insulating area and completely overlaps one of the contact pads, the contact pads forming transmit and receive rows, the cutouts in the second and third electrically conductive layers being arranged in rows corresponding to the transmit and receive rows such that there is substantially no overlap of the rows of contact pads with metal in the third electrically conductive layer.

5. The integrated circuit package substrate of claim 4, wherein the second electrically conductive layer comprises a routing layer electrically connected with the first electrically conductive layer and wherein the third electrically conductive layer comprises a ground return metal layer.

6. The integrated circuit package substrate of claim 1, wherein the second electrically conductive layer comprises a routing layer electrically connected with the first electrically conductive layer, the cutouts being arranged in rows corresponding to and aligned with the rows of contact pads.

7. An integrated circuit package substrate, comprising:

a first layer comprising a plurality of rows of electrical contacts;

a routing metal layer comprising a plurality of routing traces, the electrical contacts in the first layer being electrically connected with the respective routing traces;

a dielectric layer between the first layer and the routing metal layer with no intermediate conductive layer therebetween; and

a plurality of cutouts in the routing metal layer for reducing parasitic capacitance between the first layer and the routing metal layer, the cutouts respectively overlapping the electrical contacts and having the same or larger dimensions as the electrical contacts such that there is substantially no overlap of the rows of contact pads with metal in the routing metal layer.

8. The integrated circuit package substrate of claim 7, wherein the cutouts are arranged in rows corresponding to the rows of electrical contacts, each of the cutouts completely overlapping a corresponding one of the electrical contacts.

9. The integrated circuit package substrate of claim 8, further comprising a ground return metal layer and a second dielectric layer between the routing metal layer and the ground return metal layer, the ground return metal layer including a plurality of cutouts respectively overlapping the electrical contacts for reducing parasitic capacitance between the first layer and the ground return metal layer such that there is substantially no overlap of the rows of contact pads with metal in the ground return metal layer.

10. The integrated circuit package substrate of claim 8, wherein the rows of electrical contacts include transmit rows and receive rows operable with the routing metal layer for converting a serial data stream to or from a parallel data stream.

11. The integrated circuit package substrate of claim 8, wherein the electrical contacts are ball pads having the same dimensions as the cutouts.

12. An integrated circuit package substrate, comprising:

a first layer comprising a plurality of rows of electrical contacts;

a plurality of electrically conductive layers disposed immediately proximate the first layer;

a plurality of dielectric layers separating, respectively, the electrically conductive layers and the first layer from each other, and

a plurality of rows of cutouts formed in each of the plurality of the electrically conductive layers, each of the cutouts overlapping a corresponding one of the electrical contacts for reducing parasitic capacitance between the electrically conductive layers and the first layer such that there is substantially no overlap of the rows of electrical contacts with metal in the plurality of electrically conductive layers.

13. The integrated circuit package substrate of claim 12, wherein each of the cutouts completely overlaps a corresponding one of the electrical contacts.

14. The integrated circuit package substrate of claim 13, wherein the electrically conductive layers comprise at least a ground return metal layer and a routing metal layer, the routing metal layer comprising a plurality of routing traces, the electrical contacts in the first layer being electrically connected with the respective routing traces using electrically conductive vias.

15. The integrated circuit package substrate of claim 14, wherein each of the cutouts has the same or larger dimensions as a corresponding electrical contact with which it overlaps.

16. The integrated circuit package substrate of claim 12, wherein the electrical contacts comprise transmit rows and receive rows, and the electrically conductive layers are operable to convert a serial data stream to or from a parallel data stream.

17. The integrated circuit package substrate of claim 16, wherein each cutout completely overlaps a corresponding one of the electrical contacts.

18. The integrated circuit package of claim 16, wherein the electrical contacts comprise ball pads, the cutouts having the same dimensions as the ball pads.

19. The integrated circuit package substrate of claim 18, further comprising a plurality of vias electrically connected, respectively, to the ball pads and routing traces within the cutouts for respectively connecting the vias to one of the electrically conductive layers.