Bidirectional multiplexed RF isolator
First Claim
1. A bidirectional integrated circuit isolator for providing bidirectional data transfer of digital data signals across a voltage isolation barrier, comprising:
- an integrated circuit package having a first plurality of input/output data pins on one side of the isolation barrier and a second and corresponding plurality of input/output data pins on the other side of the isolation boundary;
first circuitry associated with the first plurality of input/output data pins and second circuitry associated with the second plurality of input/output data pins;
a communications interface for providing across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel separate from the first communications channel for communicating data from the second circuitry to the first circuitry;
the first circuitry operable to communicate information from input digital data overlapping each other in time and received on two or more of the associated first plurality of input/output data pins across the first communications channel and the second circuitry operable to receive the communicated data from the first circuitry and reconstruct the communicated data for output on the respective ones of the second plurality of input/output data pins corresponding to the two or more of the associated first plurality of input/output data pins from which the communicated data was communicated;
the second circuitry operable to communicate information from input digital data overlapping each other in time and received on two or more of the associated second plurality of input/output data pins across the second communications channel and the first circuitry operable to receive the communicated data from the second circuitry and reconstruct the communicated data for output on the respective ones of the first plurality of input/output data pins corresponding to the two or more of the associated first plurality of input/output data pins from which the communicated data was communicated; and
switching circuitry associated with each of said first and second circuitry for selecting which of the data pins associated with either of the first or second plurality of input/output data pins are input data or output data.
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Accused Products
Abstract
An isolator provides bidirectional data transfer for a plurality of communications channels. First and second dies are located on first and second sides of a voltage isolation barrier and have a first and second plurality of digital data input/output pins associated therewith. First circuitry on the first die and third circuitry on the second die serializes a plurality of parallel digital data inputs from the digital data input/output pins onto one link across the barrier and transmits synchronization clock signals associated with the digital data inputs over a link across the barrier. Second circuitry on the second die and fourth circuitry on the first die de-serializes the digital data inputs from the first link onto the second digital data input/output pins and receives the first synchronization clock signal associated with the digital data inputs on the second link.
158 Citations
24 Claims
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1. A bidirectional integrated circuit isolator for providing bidirectional data transfer of digital data signals across a voltage isolation barrier, comprising:
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an integrated circuit package having a first plurality of input/output data pins on one side of the isolation barrier and a second and corresponding plurality of input/output data pins on the other side of the isolation boundary; first circuitry associated with the first plurality of input/output data pins and second circuitry associated with the second plurality of input/output data pins; a communications interface for providing across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel separate from the first communications channel for communicating data from the second circuitry to the first circuitry; the first circuitry operable to communicate information from input digital data overlapping each other in time and received on two or more of the associated first plurality of input/output data pins across the first communications channel and the second circuitry operable to receive the communicated data from the first circuitry and reconstruct the communicated data for output on the respective ones of the second plurality of input/output data pins corresponding to the two or more of the associated first plurality of input/output data pins from which the communicated data was communicated; the second circuitry operable to communicate information from input digital data overlapping each other in time and received on two or more of the associated second plurality of input/output data pins across the second communications channel and the first circuitry operable to receive the communicated data from the second circuitry and reconstruct the communicated data for output on the respective ones of the first plurality of input/output data pins corresponding to the two or more of the associated first plurality of input/output data pins from which the communicated data was communicated; and switching circuitry associated with each of said first and second circuitry for selecting which of the data pins associated with either of the first or second plurality of input/output data pins are input data or output data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit single chip isolator for providing bidirectional data transfer for a plurality of communications channels, comprising:
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a first die located on a first side of a voltage isolation barrier in the chip having a first plurality of digital data input/output pins; a second die located on a second side of the voltage isolation barrier in the chip having a second plurality of digital data input/output pins; first circuitry located on the first die on a first side of the voltage isolation barrier for serializing a first plurality of parallel digital data inputs from the first plurality of digital data input/output pins onto a first link across the voltage isolation barrier and for transmitting a first synchronization clock signal associated with the first plurality of parallel digital data inputs over a second link across the voltage isolation barrier; second circuitry located on the second die on a second side of the voltage isolation barrier for de-serializing the serialized first plurality of parallel digital data inputs from the first link onto the second plurality of digital data input/output pins and for receiving the first synchronization clock signal associated with the first plurality of parallel digital data inputs on the second link; third circuitry located on the second die on the second side of the voltage isolation barrier for serializing a second plurality of parallel digital data inputs from the second plurality of digital data input/output pins onto a third link across the voltage isolation barrier and for transmitting a second synchronization clock signal associated with the second plurality of parallel digital data inputs over a fourth link across the voltage isolation barrier; fourth circuitry located on the first die on the first side of the voltage isolation barrier for de-serializing the serialized second plurality of parallel digital data inputs from the third link onto the first plurality of digital data input/output pins and for receiving the second synchronization clock signal associated with the second plurality of parallel digital data inputs on the fourth link; a first plurality of switches each associated with one of the first plurality of digital data input/output pins for switching an associated digital data input/output pin between the first circuitry and the fourth circuitry; and a second plurality of switches each associated with one of the second plurality of digital data input/output pins for switching an associated digital data input/output pin between the second circuitry and the third circuitry. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification