Bus protocol for transferring pixel data between chips
First Claim
1. A system for transmitting isochronous data for display, the system comprising:
- a first integrated circuit that includes a host interface;
a second integrated circuit that includes a target interface; and
a data bus coupling the host interface to the target interface and including a host data path that comprises twenty differential pairs for transmitting twenty bits of data per rising edge of a reference clock signal and twenty bits of data per falling edge of the reference clock signal,wherein, for each data phase cycle, the host interface is configured to transmit forty bits of data to the target interface via the host data path such that twenty thirty-six bit pixels may be transmitted to the target interface in eighteen data phase cycles.
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Accused Products
Abstract
One embodiment of the present invention sets forth a protocol for packing and transferring pixel data between integrated circuits. The data transfer protocol may be used between a graphics processing unit and a video output encoder unit. The data transfers may include up to 20 pixels per arbitration cycle. By packing pixel data for transfer over a bus with a relatively small set of output pins, overall package pin count is reduced, while maintaining sufficient bandwidth to carry the pixel data the output pins. By moving the analog circuitry to a separate device, linked to the GPU via the bus, noise from the GPU may be effectively mitigate through physical separation.
38 Citations
20 Claims
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1. A system for transmitting isochronous data for display, the system comprising:
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a first integrated circuit that includes a host interface; a second integrated circuit that includes a target interface; and a data bus coupling the host interface to the target interface and including a host data path that comprises twenty differential pairs for transmitting twenty bits of data per rising edge of a reference clock signal and twenty bits of data per falling edge of the reference clock signal, wherein, for each data phase cycle, the host interface is configured to transmit forty bits of data to the target interface via the host data path such that twenty thirty-six bit pixels may be transmitted to the target interface in eighteen data phase cycles. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computing device configured for transmitting isochronous data for display, the computing device comprising:
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a central processing unit coupled to a system memory; a first integrated circuit coupled to the central processing unit and including a host interface; a second integrated circuit that includes a target interface; and a data bus coupling the host interface to the target interface and including a host data path that comprises twenty differential pairs for transmitting twenty bits of data per rising edge of a reference clock signal and twenty bits of data per falling edge of the reference clock signal, wherein, for each data phase cycle, the host interface is configured to transmit forty bits of data to the target interface via the host data path such that twenty thirty-six bit pixels may be transmitted to the target interface in eighteen data phase cycles. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification