MISFET with capacitors

• US 8,050,066 B2
• Filed: 04/11/2008
• Issued: 11/01/2011
• Est. Priority Date: 05/17/2007
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ito, Hisanori, Haraguchi, Keiichi, Kamei, Satoshi, Matsui, Toshikazu
• Primary Examiner(s): Weiss; Howard
• Assistant Examiner(s): RAO, SHRINIVAS H
• Application Number:
  US12/101,959
• Publication Number:
  US 20080283889A1
• Time in Patent Office: 1,299 Days
• Field of Search: 363/71, 363/73, 363/132, 257/297, 257/298, 257/299
• US Class Current: 363/71
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between first and second potentials. Lower electrodes of the first and third capacitive elements are respectively formed by a common conductor pattern and coupled to the first potential. Lower electrodes of the second and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and coupled to the second potential. Upper electrodes of the first and second capacitive elements are respectively formed by a common conductor pattern and brought to a floating potential. Upper electrodes of the third and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and brought to a floating potential, but not coupled to the upper electrodes of the first and second capacitive elements by a conductor.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

a first capacitive element, a second capacitive element, a third capacitive element, and a fourth capacitive element which are disposed over the semiconductor substrate,

wherein the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are respectively formed by first and second electrodes opposite to each other via an insulating film interposed therebetween,

wherein the first electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are formed by respective portions of a first conductor layer, the portions being located in a first plane,

wherein the second electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are formed by respective portions of a second conductor layer, the portions being located in a second plane,

wherein the first electrodes of the first capacitive element and the third capacitive element are electrically coupled to each other through a conductor and coupled to a first potential,

wherein the first electrodes of the second capacitive element and the fourth capacitive element are electrically coupled to each other through a conductor and coupled to a second potential different from the first potential,

wherein the second electrodes of the first capacitive element and the second capacitive element are electrically coupled to each other through a conductor and brought to a floating potential,

wherein the second electrodes of the third capacitive element and the fourth capacitive element are electrically coupled to each other through a conductor and brought to a floating potential,

wherein the second electrodes of the first capacitive element and the second capacitive element, and the second electrodes of the third capacitive element and the fourth capacitive element are not coupled by a conductor,

wherein the first capacitive element is connected in series with the second capacitive element to form a first series circuit, and the third capacitive element is connected in series with the fourth capacitive element to form a second series circuit, and

wherein the first series circuit is connected in parallel with the second series circuit.

2. The semiconductor device according to claim 1, wherein the first conductor layer is disposed over the semiconductor substrate, and the second conductor layer is disposed above or below the first conductor layer.

3. The semiconductor device according to claim 2, wherein each of the first conductor layer and the second conductor layer comprises a respective metal layer.

4. The semiconductor device according to claim 3, wherein the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are of MIM type capacitive elements respectively.

5. The semiconductor device according to claim 4, wherein the second conductor layer is disposed below the first conductor layer.

6. The semiconductor device according to claim 2, wherein each of the first conductor layer and the second conductor layer comprises a respective silicon layer.

7. The semiconductor device according to claim 6, wherein the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are of PIP type capacitive elements respectively.

8. The semiconductor device according to claim 7, wherein the second conductor layer is disposed above the first conductor layer.

9. The semiconductor device according to claim 2, wherein the conductor layer of the first and second conductor layers which is disposed lower comprises an impurity diffusion layer formed within the semiconductor substrate.

10. The semiconductor device according to claim 9, wherein the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are of MOS type capacitive elements respectively.

11. The semiconductor device according to claim 9, wherein the first electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element comprise the impurity diffusion layer formed in the semiconductor substrate.

12. The semiconductor device according to claim 2, wherein the first electrodes of the first capacitive element and the third capacitive element are respectively formed by a first conductor pattern of the first conductor layer, the first electrodes of the second capacitive element and the fourth capacitive element are respectively formed by a second conductor pattern of the first conductor layer, the second conductor pattern being electrically separated from the first conductor pattern, and the second electrodes of the first capacitive element and the second capacitive element are respectively formed by a third conductor pattern of the second conductor layer, and the second electrodes of the third capacitive element and the fourth capacitive element are respectively formed by a fourth conductor pattern of the second conductor layer, the fourth conductor pattern being electrically separated from the third conductor pattern.

13. The semiconductor device according to claim 12, wherein the third conductor pattern and the fourth conductor pattern extend so as to intersect with the first conductor pattern and the second conductor pattern, and the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are respectively formed in areas where the third and the fourth conductor patterns cross the first and second conductor patterns.

14. The semiconductor device according to claim 1, wherein one of the first potential and the second potential is a source potential and the other is a ground potential.

15. The semiconductor device according to claim 1, wherein the first capacitive element and the second capacitive element are coupled in series, the third capacitive element and the fourth capacitive element are coupled in series, and a series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between the first potential and the second potential.

16. A semiconductor device comprising:

a circuit formed over a semiconductor substrate, the circuit including a plurality of series circuits each comprising a pair of first and second capacitive elements, the series circuits being coupled in parallel between a first potential and a second potential different from the first potential,

wherein the first and second capacitive elements of the series circuits are respectively formed by first and second electrodes opposite to each other via an insulating film interposed therebetween,

wherein the first electrodes of the first capacitive elements of the series circuits are respectively electrically coupled to one another through conductors and coupled to the first potential,

wherein the first electrodes of the second capacitive elements of the series circuits are respectively electrically coupled to one another through conductors and coupled to the second potential,

wherein the second electrodes of the first capacitive elements and the second electrodes of the second capacitive elements in the respective series circuits are electrically coupled to one another through conductors and brought to a floating potential, respectively,

wherein the first electrodes of the first and second capacitive elements of the series circuits are formed by respective portions of a first conductor layer, the portions being located in a first plane,

wherein the second electrodes of the first and second capacitive elements of the series circuits are formed by respective portions of a second conductor layer, the portions being located in a second plane, and

wherein the second electrodes of the first and second capacitive elements of each series circuit are not coupled by conductors to the second electrodes of the first and second capacitive elements of the other series circuits.

17. The semiconductor device according to claim 16, wherein the first electrodes of the first and second capacitive elements of the series circuits comprise a first conductor layer disposed over the semiconductor substrate, and the second electrodes of the second capacitive elements of the series circuits comprise a second conductor layer disposed in a layer above or below the first conductor layer.

18. The semiconductor device according to claim 17, wherein the first and second capacitive elements are of MIM type, PIP type or MOS type capacitive elements respectively.

19. The semiconductor device according to claim 17, wherein the second conductor layer is formed in a layer below the first conductor layer, and the second electrodes of the first capacitive elements and the second electrodes of the second capacitive elements in the respective series circuits are respectively electrically coupled to one another through a third conductor layer disposed below the second conductor layer.

20. The semiconductor device according to claim 19, wherein the first capacitive elements and the second capacitive elements of the series circuits are of MIM type capacitive elements respectively, and the MIM type capacitive elements are arranged in an array above a main surface of the semiconductor substrate.

21. The semiconductor device according to claim 16, wherein one of the first potential and the second potential is a source potential and the other is a ground potential.

22. The semiconductor device according to claim 16, wherein the first capacitive elements and the second capacitive elements of the series circuits are of MIM type capacitive elements respectively, and the MIM type capacitive elements are disposed over an upper portion of an area in which semiconductor integrated circuits are disposed on a main surface of the semiconductor substrate.

23. A semiconductor device, comprising:

a first capacitive element, a second capacitive element, a third capacitive element and a fourth capacitive element, the first capacitive element comprising a first upper electrode, a first lower electrode and a first capacitive insulating film, the second capacitive element comprising a second upper electrode, a second lower electrode and a second capacitive insulating film, the third capacitive element comprising a third upper electrode, a third lower electrode and a third capacitive insulating film and the fourth capacitive element comprising a fourth upper electrode, a fourth lower electrode and a fourth capacitive insulating film, the lower electrodes of first, second, third, and fourth capacitive elements being located in a first plane, and the upper electrodes of the first, second, third, and fourth capacitive elements being located in a second plane,

the semiconductor device further comprising;

a semiconductor substrate;

a semiconductor element formed over the semiconductor substrate;

a wiring layer and a first interlayer insulating film formed over the semiconductor element;

a second interlayer insulating film formed over the wiring layer and the first interlayer insulating film;

a first connecting wiring and a second connecting wiring formed in the second interlayer insulating film;

a third interlayer insulating film formed over the first connecting wiring and the second connecting wiring;

a first plug, a second plug, a third plug and a fourth plug formed in the third interlayer insulating film, the first plug and the second plug being electrically coupled to the first connecting wiring and the third plug and the fourth plug being electrically coupled to the second connecting wiring;

a fourth interlayer insulating film formed over the first plug, the second plug, the third plug, and the fourth plug;

the first lower electrode, the second lower electrode, the third lower electrode, and the fourth lower electrode formed in the fourth interlayer insulating film, the first lower electrode being electrically coupled to the first plug, the second lower electrode being electrically coupled to the second plug, the third lower electrode being electrically coupled to the third plug and the fourth lower electrode being electrically coupled to the fourth plug;

the first capacitive insulating film formed over the first lower electrode, the second capacitive insulating film formed over the second lower electrode, the third capacitive insulating film formed over the third lower electrode and the fourth capacitive insulating film formed over the fourth lower electrode, the first capacitive insulating film, the second capacitive insulating film, the third capacitive insulating film, and the fourth capacitive insulating film formed of respective portions of an insulating film;

the first upper electrode formed over the first capacitive insulating film, the second upper electrode formed over the second capacitive insulating film, the third upper electrode formed over the third capacitive insulating film, and the fourth upper electrode formed over the fourth capacitive insulating film, the first upper electrode, the second upper electrode, the third upper electrode and the fourth upper electrode formed of respective portions of a conductive film; and

a first upper wiring layer formed over the first upper electrode and the third upper electrode to electrically couple the first upper electrode and the third upper electrode, and a second upper wiring layer formed over the second upper electrode and the fourth upper electrode to electrically couple the second upper electrode and the fourth upper electrode,

wherein the first lower electrode and the second lower electrode are electrically coupled to each other through the first plug, the first connecting wiring, and the second plug, and brought to a first floating potential,

wherein the third lower electrode and the fourth lower electrode are electrically coupled to each other through the third plug, the second connecting wiring, and the fourth plug, and brought to a second floating potential, and

wherein the first upper electrode and the third upper electrode, and the second upper electrode and the fourth upper electrode are not coupled by a conductor.

24. The semiconductor device according to claim 23,

wherein the first connecting wiring and the second connecting wiring extend in a first direction, and

wherein the first upper wiring and the second upper wiring extend in a second direction perpendicular to the first direction.

25. The semiconductor device according to claim 23,

wherein a planar area of the first capacitive insulating film, the second capacitive insulating film, the third capacitive insulating film, and the fourth capacitive insulating film and that of the first upper electrode, the second upper electrode, the third upper electrode and the fourth upper electrode are equal to each other and are larger than a planar area of the first lower electrode, the second lower electrode, the third lower electrode, and the fourth lower electrode, and

wherein the first capacitive insulating film, the second capacitive insulating film, the third capacitive insulating film, and the fourth capacitive insulating film overlap the first lower electrode, the second lower electrode, the third lower electrode, and the fourth lower electrode, respectively in a plane.

26. The semiconductor device according to claim 23,

wherein the first upper wiring layer is formed so as to cover the first capacitive insulating film and the third capacitive insulating film, and the first upper electrode and the third upper electrode, and

wherein the second upper wiring layer is formed so as to cover the second capacitive insulating film and the fourth capacitive insulating film, and the second upper electrode and the fourth upper electrode.