Semiconductor memory device and semiconductor memory device operation method

• US 8,050,108 B2
• Filed: 11/03/2009
• Issued: 11/01/2011
• Est. Priority Date: 11/05/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shirai, Takayuki, Naga, Shunsaku, Shimogawa, Kenjiyu, Furuta, Hiroshi
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US12/611,589
• Publication Number:
  US 20100110814A1
• Time in Patent Office: 728 Days
• Field of Search: 365/189.04, 365/189.11, 365/207, 365/194
• US Class Current: 365/189.04
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit (24) is provided between each bit line (21) and each sense amplifier (26). In writeback, the switch circuits are turned on at staggered time points. In readout, the switch circuits are turned on to read memory cell data to the sense amplifiers while the sense amplifiers are turned off, and the switch circuits are then turned off once. After that, the sense amplifiers are turned on to amplify the read data. The switch circuits are subsequently divided into groups and turned on again to write back the data amplified by the sense amplifiers to the memory cells. The switch circuits are divided into groups to be turned on at staggered time points during the writeback, to thereby avoid concentration of the writeback current in one time period.

Claims

1. A semiconductor memory device including:

a plurality of word lines;

a plurality of bit lines which are provided in a direction intersecting the plurality of word lines;

a plurality of memory cells which are arranged in a matrix pattern that corresponds to intersections between the plurality of word lines and the plurality of bit lines;

a plurality of sense amplifiers which are associated with the plurality of bit lines on a one-on-one basis;

a plurality of switch circuits each of which belongs to one of first to n-th (n is an integer equal to or larger than

     2) groups, and which are associated with the plurality of bit lines and with the plurality of sense amplifiers on a one-on-one basis, each switch circuit connecting its associated bit line and sense amplifier to each other when turned on; and

a timing control section for controlling at least timing of the sense amplifiers and the switch circuits which, in reading stored data out of the memory cells, executes control in which the plurality of sense amplifiers are disabled while the plurality of switch circuits are turned on for a given period of time, the plurality of switch circuits are turned off and then the plurality of sense amplifiers are enabled, and, when a given period of time elapses since the relevant sense amplifiers are enabled, the switch circuits belonging to the first to n-th groups are sequentially turned on group by group at given time intervals.

2. A semiconductor memory device according to claim 1, wherein the timing control section executes control in which, when a given period of time elapses since the sense amplifiers are enabled, the switch circuits belonging to the first to n-th groups are sequentially turned on group by group at given time intervals, and the switch circuits belonging to the first to n-th groups are turned off when a given period of time elapses since the switch circuits that belong to the last group are turned on.

3. A semiconductor memory device according to claim 1, wherein, in turning on the switch circuits belonging to the first to n-th groups sequentially group by group at given time intervals, the timing control section executes control in which the switch circuits of a preceding group are turned off before the switch circuits of the next group are turned on, so that a time period in which the switch circuits of one group are on is prevented from overlapping with a time period in which the switch circuits of another group is on.

4. A semiconductor memory device according to claim 1,

wherein each of the plurality of sense amplifiers belongs to one of first to n-th groups that corresponds to the switch circuit group of its associated switch circuit, and

wherein the timing control section executes control in which, after the plurality of switch circuits are turned off, the sense amplifiers are sequentially enabled group by group at given time intervals, and, when a given period of time elapses since the sense amplifiers of one group are enabled, the switch circuits of the corresponding group are turned on.

5. A semiconductor memory device according to claim 4, wherein, in sequentially enabling the sense amplifiers group by group at given time intervals, the timing control section turns off the sense amplifiers and switch circuits belonging to a group whose sense amplifiers are previously enabled, and then enables the sense amplifiers of the next group.

6. A semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises a dynamic random access memory.

7. A semiconductor memory device according to claim 1,

wherein the timing control section includes a timing controller and a switch control circuit,

wherein the timing controller generates a sense amplifier enable signal, which controls enabled/disabled state of the sense amplifiers, and a switch control pulse, which serves as a reference for on/off of the switch circuits, and

wherein the switch control circuit controls the on/off of the plurality of switch circuits group by group, based on the sense amplifier enable signal and the switch control pulse.

8. An operation method of a semiconductor memory device comprising:

a plurality of word lines;

a plurality of bit lines which are provided in a direction intersecting the plurality of word lines;

a plurality of memory cells which are arranged in a matrix pattern that corresponds to intersections between the plurality of word lines and the plurality of bit lines;

a plurality of sense amplifiers which are associated with the plurality of bit lines on a one-on-one basis; and

a plurality of switch circuits which, when turned on, connect the plurality of bit lines and the plurality of sense amplifiers to each other,

the method comprising;

disabling the plurality of sense amplifiers while turning on the plurality of switch circuits for a given period of time;

turning off the plurality of switch circuits and then enabling the plurality of sense amplifiers; and

when a given period of time elapses since the sense amplifiers are enabled, dividing the plurality of switch circuits into a plurality of groups so that the switch circuits are sequentially turned on group by group at given time intervals.

9. A semiconductor memory device operation method according to claim 8,

wherein the semiconductor memory device comprises a destructive readout semiconductor memory device, and

wherein the operation comprises a readout operation and a data writeback operation which accompanies the readout operation.