Multi-column addressing mode memory system including an integrated circuit memory device

• US 8,050,134 B2
• Filed: 02/02/2011
• Issued: 11/01/2011
• Est. Priority Date: 09/30/2004
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Bellows, Chad A., Richardson, Wayne S., Lai, Lawrence, Ware, Frederick A.
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US13/019,785
• Publication Number:
  US 20110153932A1
• Time in Patent Office: 272 Days
• Field of Search: 711/5, 711/105, 711/154, 365/189.04, 365/230.03, 365/230.06, 365/233
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Claims

1. An integrated circuit memory device, comprising:

a storage array having storage cells arranged in plural rows and plural columns;

a row decoder to select a row of storage cells within the storage array;

column decoder circuitry to select one or more of the plural columns in the selected row in response to one or more externally supplied column addresses; and

an interface to couple the integrated circuit memory device with an external interconnect;

where

a minimum time interval comprising a minimum number of clock cycles must elapse between successive accesses to an open row of storage cells in the storage array, and

the memory device outputs data read from the open row, in response to two different externally supplied column addresses, to the external interconnect via the interface during a time period less than twice the minimum time interval.

2. The integrated circuit memory device of claim 1, where the two different externally supplied column addresses are both received together in a single request packet by the memory device.

3. The integrated circuit memory device of claim 1, where the two different externally supplied column addresses are simultaneously received by the memory device.

4. The integrated circuit memory device of claim 1, where the column decoder circuitry is to concurrently select one or more of the plural columns in the selected row in response to one or more externally supplied column addresses.

5. The integrated circuit memory device of claim 1, where the storage array includes two banks, and where the column decoder circuitry includes a column decoder for each bank.

6. The integrated circuit memory device of claim 5, where each column decoder is a dual column decoder.

7. The integrated circuit memory device of claim 1, where the two different externally supplied column addresses are supplied to the memory device independently of one another.

8. The integrated circuit memory device of claim 1, where the plural columns include at least thirty-two columns.

9. The integrated circuit memory device of claim 1, further comprising multiple modes of operation including a first mode of operation in which a set of read data is output from the open row within the time period, and a second mode of operation in which two columns of read data are output respectively in response to the two different externally supplied column addresses within the time period, the two columns of read data in the second mode each representing smaller data granularity than the set of read data in the first mode.

10. The integrated circuit memory device of claim 1, the storage array comprising multiple independently addressable banks.

11. The integrated circuit memory device of claim 1, further comprising circuitry to receive a request for a masked read in association with at least one of the two different externally supplied column addresses.

12. The integrated circuit memory device of claim 1, where the memory device outputs read data from the open row, in response to four different externally supplied column addresses, to the external interconnect via the interface during a time period less than twice the minimum time interval.

13. The integrated circuit memory device of claim 1, where the interface includes plural contacts to exchange data with a remote memory controller via the external interconnect, and where the integrated circuit memory device is to output data associated with a first one of the two different externally supplied column addresses on a first subset of the plural contacts associated with the external interconnect and to output data associated with a second one of the two different externally supplied column addresses on a second subset of the plural contacts associated with the external interconnect, the first and second subsets being mutually exclusive.

14. The integrated circuit memory device of claim 1, further comprising at least one contact to exchange data with a remote memory controller via the external interface, and where the integrated circuit memory device is to output data associated with each of the two different externally supplied column addresses in a time multiplexed manner over the at least one contact.

15. The integrated circuit memory device of claim 14, further comprising a pipeline register to adjust timing of at least a portion of the data output in a time multiplexed manner over the at least one contact.

16. The integrated circuit memory device of claim 1, further comprising circuitry to mask a portion of at least one addressed column in response to an externally provided mask command.

17. The integrated circuit memory device of claim 1, further comprising circuitry to receive a single request packet via the interface and to generate from the single request packet the two different externally supplied column addresses.

18. An integrated circuit memory device, comprising:

a storage array having storage cells arranged in plural rows and plural columns;

a row decoder to select a row of storage cells within the storage array;

where a minimum time interval comprising a minimum number of clock cycles must elapse between successive accesses to an open row of storage cells in the storage array; and

means for outputting read data from the open row and from the integrated circuit memory device in response to two different externally supplied column addresses within a time period less than twice the minimum time interval.

19. The integrated circuit memory device of claim 18, further comprising means for generating at least two different externally supplied column addresses from a single request packet, the means for outputting responsive to the means for generating so that the read data output from the open row represents the at least two different externally supplied column addresses generated from the single request packet.

20. A method of operation in an integrated circuit memory device, the integrated circuit memory device having a storage array having storage cells arranged in plural rows and plural columns and a row decoder to select a row of storage cells within the storage array, the integrated circuit memory device further characterized by a minimum time interval comprising a minimum number of clock cycles must elapse between successive accesses to an open row of storage cells in the storage array, the method comprising:

obtaining two or more externally supplied column addresses;

opening a row of the storage array;

selecting two or more columns in the open row in response to the respective externally supplied column addresses; and

outputting read data associated with each of the selected two or more columns from the open row during a time period less than twice the minimum time interval.

21. The method of claim 20, further comprising generating at least two different externally supplied column addresses from a single request packet, such that the read data output from the open row represents the at least two different externally supplied column addresses generated from the single request packet.

22. The method of claim 20, further comprising simultaneously accessing the two or more columns in the open row to output the read data.

23. The method of claim 20, where outputting the read data associated with each of the selected two or more columns includes simultaneously outputting the read data associated with at least two of the selected two or more columns to an external interconnect.