Result path sharing between a plurality of execution units within a processor

• US 8,051,275 B2
• Filed: 06/01/2009
• Issued: 11/01/2011
• Est. Priority Date: 06/01/2009
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Allué, Conrado Blasco, Williamson, David James
• Primary Examiner(s): Faherty; Corey S.
• Application Number:
  US12/457,124
• Publication Number:
  US 20100306505A1
• Time in Patent Office: 883 Days
• Field of Search: None
• US Class Current: 712/214
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Abstract

A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution cluster 10 determines future availability of a result bus 22, 24 for an instruction to be issued (or recently issued) using a known cycle count for that instruction. The availability is tracked for each result bus using a mask register 32 storing a mask value within which each bit position indicates the availability or non-availability of that result bus at a particular processing cycle in the future. The mask value is left shifted each processing cycle.

Claims

1. Apparatus for processing data, said apparatus comprising:

a plurality of execution units responsive to program instructions to execute data processing operations to generate processing results;

at least one shared result path coupled to said plurality of execution units to carry said processing results generated by said plurality of execution units; and

issue circuitry responsive to said program instructions to issue said data processing operations to said plurality of execution units for execution;

wherein

said issue circuitry controls execution of a given processing operation having a known processing time upon a given execution unit to generate a given processing result in dependence upon a determination using said known processing time and availability of said at least one shared result path to carry said given processing result when generated by said given execution unit, wherein said issue circuitry is responsive to a number of processing cycles that will be required to execute said given processing operation to determine a processing cycle in which said given processing result will be generated if issued and completely executed and at least does not permit complete execution of said given processing operation to generate said given processing result unless said at least one shared result path will be available to carry said given processing result when generated, wherein said given processing operation is issued independently of availability of said at least one shared result path but execution of said given processing operation is cancelled if said issue circuitry determines that said at least one shared result path will be unavailable when said given processing result will be generated.

2. Apparatus as claimed in claim 1, wherein said issue circuitry controls issue for execution of said given processing operation in dependence upon said availability.

3. Apparatus as claimed in claim 1, wherein said issue circuitry tracks future use of said at least one shared result path by already issued processing operations.

4. Apparatus as claimed in claim 3, wherein for each of said at least one result path, said issue circuitry includes a mask register storing a mask value having bit positions representing availability of said at least one shared result path in future processing cycles.

5. Apparatus as claimed in claim 4, wherein when said issue circuitry issues said given processing operation it sets to a predetermined value of a bit position within said mask value corresponding to a future processing cycle in which said given processing operation will generate said given processing result.

6. Apparatus as claimed in claim 5, wherein said mask value is shifted each processing cycle to update bit values of said mask value to positions corresponding to how many processing cycles in the future those bit values represent.

7. Apparatus as claimed in claim 4, wherein said mask value has a bit-length corresponding to a maximum number of processing cycles needed by any one of said plurality of execution units to generate said given processing result.

8. Apparatus as claimed in claim 1, comprising a plurality of shared result paths and wherein there are fewer shared result paths than execution units.

9. Apparatus as claimed in claim 8, wherein said issue circuitry determines availability of a shared result path from any of said plurality of shared result paths.

10. Apparatus as claimed in claim 1, wherein said issue circuitry determines if another processing operation for issue in a common processing cycle conflicts for use of said at least one result path to carry their processing result and selects one of said given processing operation and said another processing operation for issue if said at least one shared result path is available.

11. Apparatus as claimed in claim 1, wherein said at least one shared result path is a shared result bus within a processor.

12. Apparatus as claimed in claim 11, wherein said processor is an out-of-order processor.

13. Apparatus as claimed in claim 1, comprising a register store, said plurality of execution units writing respective processing results to said register store, said at least one shared result path being coupled to at least one shared write port of said register store.

14. Apparatus for processing data, said apparatus comprising:

a plurality of execution means responsive to program instructions for executing data processing operations, for generating processing results;

at least one shared result path means, coupled to said plurality of execution units for carrying said processing results generated by said plurality of execution means; and

issue means, responsive to said program instructions for issuing said data processing operations to said plurality of execution means for execution;

wherein

said issue means controls execution of a given processing operation having a known processing time upon a given execution means to generate a given processing result in dependence upon a determination using said known processing time and availability of said at least one shared result path means to carry said given processing result when generated by said given execution means, wherein said issue means is responsive to a number of processing cycles that will be required to execute said given processing operation to determine a processing cycle in which said given processing result will be generated if issued and completely executed and at least does not permit complete execution of said given processing operation to generate said given processing result unless said at least one shared result path means will be available to carry said given processing result when generated, and said given processing operation is issued independently of availability of said at least one shared result path means but execution of said given processing operation is cancelled if said issue means determines that said at least one shared result path means will be unavailable when said given processing result will be generated.

15. A method of processing data, said method comprising the steps of:

using, in response to program instructions, a plurality of execution units to execute data processing operations to generate processing results;

carrying said processing results generated by said plurality of execution units on at least one shared result path coupled to said plurality of execution units;

issuing, in response to said program instructions, said data processing operations to said plurality of execution units for execution;

controlling execution of a given processing operation having a known processing time upon a given execution unit to generate a given processing result in dependence upon a determination using said known processing time and availability of said at least one shared result path to carry said given processing result when generated by said given execution unit; and

determining, in response to a number of processing cycles that will be required to execute said given processing operation, a processing cycle in which said given processing result will be generated if issued and completely executed and at least not permitting complete execution of said given processing operation to generate said given processing result unless said at least one shared result path will be available to carry said given processing result when generated, wherein said issuing step issues said given processing operation independently of availability of said at least one shared result path but execution of said given processing operation is cancelled if said determining step determines that said at least one shared result path will be unavailable when said given processing result will be generated.