Timing-aware test generation and fault simulation

• US 8,051,352 B2
• Filed: 04/27/2007
• Issued: 11/01/2011
• Est. Priority Date: 04/27/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Lin, Xijiang, Wang, Chen, Rajski, Janusz, Kassab, Mark, Tsai, Kun-Han
• Primary Examiner(s): Gaffin; Jeffrey A
• Assistant Examiner(s): NGUYEN, STEVE N
• Application Number:
  US11/796,374
• Publication Number:
  US 20070288822A1
• Time in Patent Office: 1,649 Days
• Field of Search: 714/738
• US Class Current: 714/738
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318328 for delay tests
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30

Abstract

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Claims

1. A method of generating test patterns for testing an integrated circuit, comprising:

identifying two or more possible fault propagation paths in an integrated circuit design, the possible fault propagation paths being capable of propagating a fault effect of a targeted slow-to-rise transition fault or slow-to-fall transition fault to an observation point in the integrated circuit design;

selecting one of the possible fault propagation paths using a weighted random selection procedure;

generating test pattern values that propagate the fault effect of the targeted slow-to-rise transition fault or slow-to-fall transition fault on the selected fault propagation path; and

storing the test pattern values.

2. The method of claim 1, wherein the weighted random selection procedure favors fault propagation paths with longer path delays over fault propagation paths with shorter path delays.

3. The method of claim 1, wherein the weighted random selection procedure favors fault propagation paths with shorter path delays over fault propagation paths with longer path delays.

4. The method of claim 1, further comprising computing weights for each of the possible fault propagation paths.

5. The method of claim 4, wherein the computed weight for a respective one of the possible fault propagation paths indicates the probability that the respective one of the possible fault propagation paths will be selected by the weighted random selection procedure.

6. The method of claim 4, wherein the act of computing weights comprises computing a weight w_i, for a respective possible fault propagation path i as follows:

7. The method of claim 4, wherein the act of computing weights comprises computing a weight w_i, for a respective possible fault propagation path i as follows:

8. The method of claim 1, wherein the method further comprises computing propagation times for one or more gates in the possible fault propagation paths, and wherein the weighted random selection procedure is based at least in part on the computed propagation times.

9. The method of claim 8, wherein the act of computing the propagation times comprises using timing information from an SDF file.

10. The method of claim 1, further comprising selecting a fault activation condition for activating the targeted slow-to-rise transition fault or slow-to-fall transition fault using a weighted random selection procedure that favors fault activation conditions having longer arrival times over fault activation conditions having shorter arrival times.

11. The method of claim 1, further comprising selecting a fault activation condition for activating the targeted slow-to-rise transition fault or slow-to-fall transition fault using a weighted random selection procedure that favors fault activation conditions having shorter arrival times over fault activation conditions having longer arrival times.

12. The method of claim 1, wherein the weighted random selection procedure is based at least in part on a propagation time of one of the possible fault propagation paths and a sum of propagation times of the possible fault propagation paths.

13. One or more computer-readable storage media storing test pattern values generated by a method, the method comprising:

identifying two or more possible fault propagation paths in an integrated circuit design, the possible fault propagation paths being capable of propagating a fault effect of a targeted slow-to-rise transition fault or slow-to-fall transition fault to an observation point in the integrated circuit design;

selecting one of the possible fault propagation paths using a weighted random selection procedure;

generating test pattern values that propagate the fault effect of the targeted slow-to-rise transition fault or slow-to-fall transition fault on the selected fault propagation path; and

storing the test pattern values.

14. One or more computer-readable storage media storing computer-executable instructions for causing a computer to perform a method, the method comprising:

identifying two or more possible fault propagation paths in an integrated circuit design, the possible fault propagation paths being capable of propagating a fault effect of a targeted slow-to-rise transition fault or slow-to-fall transition fault to an observation point in the integrated circuit design;

selecting one of the possible fault propagation paths using a weighted random selection procedure; and

generating test pattern values that propagate the fault effect of the targeted slow-to-rise transition fault or slow-to-fall transition fault on the selected fault propagation path.

15. The one or more computer-readable storage media of claim 14, wherein the weighted random selection procedure favors fault propagation paths with longer path delays over fault propagation paths with shorter path delays.

16. The one or more computer-readable storage media of claim 14, wherein the weighted random selection procedure favors fault propagation paths with shorter path delays over fault propagation paths with longer path delays.

17. The one or more computer-readable storage media of claim 14, wherein the method further comprises computing weights for each of the possible fault propagation paths.

18. The one or more computer-readable storage media of claim 17, wherein the computed weight for a respective one of the possible fault propagation paths indicates the probability that the respective one of the possible fault propagation paths will be selected by the weighted random selection procedure.

19. The one or more computer-readable storage media of claim 17, wherein the act of computing weights comprises computing a weight w_i, for a respective possible fault propagation path i as follows:

20. The one or more computer-readable storage media of claim 17, wherein the act of computing weights comprises computing a weight w_i , for a respective possible fault propagation path i as follows:

21. The one or more computer-readable storage media of claim 14, wherein the method further comprises computing propagation times for one or more gates in the possible fault propagation paths, and wherein the weighted random selection procedure is based at least in part on the computed propagation times.

22. The one or more computer-readable storage media of claim 21, wherein the act of computing the propagation times comprises using timing information from an SDF file.

23. The one or more computer-readable storage media of claim 14, wherein the method further comprises selecting a fault activation condition for activating the targeted slow-to-rise transition fault or slow-to-fall transition fault using a weighted random selection procedure that favors fault activation conditions having longer arrival times over fault activation conditions having shorter arrival times.

24. The one or more computer-readable storage media of claim 14, wherein the weighted random selection procedure is based at least in part on a propagation time of one of the possible fault propagation paths and a sum of propagation times of the possible fault propagation paths.