Logic synthesis of multi-level domino asynchronous pipelines

• US 8,051,396 B2
• Filed: 05/04/2009
• Issued: 11/01/2011
• Est. Priority Date: 11/22/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Fulcrum Microsystems, Inc. (Intel Corporation)
• Inventors: Beerel, Peter, Lines, Andrew, Davies, Michael
• Primary Examiner(s): Kik; Phallaka
• Application Number:
  US12/435,270
• Publication Number:
  US 20090217232A1
• Time in Patent Office: 911 Days
• Field of Search: 716/104, 716/114, 716/132
• US Class Current: 716/104
• CPC Class Codes: G06F 30/35 Delay-insensitive circuit design, e.g. asynchronous or self-timed

Abstract

Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

Claims

1. A computer-implemented method for synthesizing a circuit which includes asynchronous logic from a netlist generated by a synchronous computer-aided design (CAD) tool, comprising using one or more computing devices to perform the following:

converting synchronous logic gates represented by the netlist to asynchronous logic gates;

replacing clock circuitry represented by the netlist with asynchronous control circuitry and completion control circuitry thereby generating a plurality of asynchronous pipelines including the asynchronous logic gates;

inserting a plurality of buffers corresponding to a specific design template into selected ones of the asynchronous pipelines to balance the asynchronous pipelines thereby meeting a plurality of performance constraints; and

removing selected ones of the buffers in a manner dependent on the specific design template to reduce overhead associated with the asynchronous logic while substantially meeting the plurality of performance constraints.

2. The method of claim 1 wherein removal of the selected buffers is accomplished using one of an integer linear programming (ILP) technique, a mixed-integer linear programming (MILP) technique, and a linear programming (LP) technique.

3. The method of claim 1 further comprising generating the netlist using the synchronous CAD tool.

4. The method of claim 3 wherein the netlist originates from a register transfer language (RTL) specification.

5. The method of claim 1 further comprising performing logic synthesis on the netlist to generate the synchronous logic gates.

6. The method of claim 1 further comprising selecting portions of synchronous logic represented by the netlist for conversion to the asynchronous logic.

7. The method of claim 1 wherein converting the synchronous logic gates to the asynchronous logic gates comprises replacing single-rail logic gates with dual-rail equivalents.

8. The method of claim 7 further comprising deriving the single-rail logic gates from a library of dual-rail logic gates.

9. The method of claim 8 wherein deriving the single-rail logic gates from the library of dual-rail logic gates comprises mapping dual-rail timing arcs to synchronous equivalents.

10. The method of claim 1 wherein the asynchronous logic gates comprise domino logic gates, and the asynchronous logic comprises multi-level domino logic.

11. A computer program product for synthesizing a circuit which includes asynchronous logic from a netlist generated by a synchronous computer-aided design (CAD) tool, the computer program product comprising one or more non-transitory computer-readable media having computer program instructions stored therein configured, when executed by one or more computing devices, to cause the one or more computing devices to:

convert synchronous logic gates represented by the netlist to asynchronous logic gates;

replace clock circuitry represented by the netlist with asynchronous control circuitry and completion control circuitry thereby generating a plurality of asynchronous pipelines including the asynchronous logic gates;

insert a plurality of buffers corresponding to a specific design template into selected ones of the asynchronous pipelines to balance the asynchronous pipelines thereby meeting a plurality of performance constraints; and

remove selected ones of the buffers in a manner dependent on the specific design template to reduce overhead associated with the asynchronous logic while substantially meeting the plurality of performance constraints.

12. The computer program product of claim 11 wherein the computer program instructions are configured to cause the one or more computing devices to remove the selected buffers using one of an integer linear programming (ILP) technique, a mixed-integer linear programming (MILP) technique, and a linear programming (LP) technique.

13. The computer program product of claim 11 wherein the computer program instructions are further configured to cause the one or more computing devices to generate the netlist using the synchronous CAD tool.

14. The computer program product of claim 13 wherein the netlist originates from a register transfer language (RTL) specification.

15. The computer program product of claim 11 wherein the computer program instructions are further configured to cause the one or more computing devices to perform logic synthesis on the netlist to generate the synchronous logic gates.

16. The computer program product of claim 11 wherein the computer program instructions are further configured to cause the one or more computing devices to select portions of synchronous logic represented by the netlist for conversion to the asynchronous logic.

17. The computer program product of claim 11 wherein the computer program instructions are configured to cause the one or more computing devices to convert the synchronous logic gates to the asynchronous logic gates by replacing single-rail logic gates with dual-rail equivalents.

18. The computer program product of claim 17 wherein the computer program instructions are further configured to cause the one or more computing devices to derive the single-rail logic gates from a library of dual-rail logic gates.

19. The computer program product of claim 18 wherein the computer program instructions are configured to cause the one or more computing devices to derive the single-rail logic gates from the library of dual-rail logic gates by mapping dual-rail timing arcs to synchronous equivalents.

20. The computer program product of claim 11 wherein the asynchronous logic gates comprise domino logic gates, and the asynchronous logic comprises multi-level domino logic.