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Logic synthesis of multi-level domino asynchronous pipelines

  • US 8,051,396 B2
  • Filed: 05/04/2009
  • Issued: 11/01/2011
  • Est. Priority Date: 11/22/2004
  • Status: Expired due to Fees
First Claim
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1. A computer-implemented method for synthesizing a circuit which includes asynchronous logic from a netlist generated by a synchronous computer-aided design (CAD) tool, comprising using one or more computing devices to perform the following:

  • converting synchronous logic gates represented by the netlist to asynchronous logic gates;

    replacing clock circuitry represented by the netlist with asynchronous control circuitry and completion control circuitry thereby generating a plurality of asynchronous pipelines including the asynchronous logic gates;

    inserting a plurality of buffers corresponding to a specific design template into selected ones of the asynchronous pipelines to balance the asynchronous pipelines thereby meeting a plurality of performance constraints; and

    removing selected ones of the buffers in a manner dependent on the specific design template to reduce overhead associated with the asynchronous logic while substantially meeting the plurality of performance constraints.

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