Three-dimensional integrated circuits with protection layers

• US 8,053,277 B2
• Filed: 09/09/2010
• Issued: 11/08/2011
• Est. Priority Date: 12/19/2006
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Tu, Hung-Jung, Chiou, Wen-Chih, Wu, Weng-Jin, Yang, Ku-Feng
• Primary Examiner(s): Smith; Zandra
• Application Number:
  US12/878,112
• Publication Number:
  US 20100330743A1
• Time in Patent Office: 425 Days
• Field of Search: 438/108, 438/109, 438/127, 438/456, 257/E21.511, 257/E21.503
• US Class Current: 438/108
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05157 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: Y10S 148/164 : Three dimensional processing

Abstract

A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.

Claims

1. A method comprising:

providing a wafer comprising a first die and a second die, each comprising a first bonding pad on a top surface of the corresponding first and second dies;

providing a third die and a fourth die each comprising a first surface and a second surface opposite the first surface;

stacking the third die on the first die, and the fourth die on the second die, wherein a second bonding pad on the first surface of each of the third and the fourth dies is bonded to the first bonding pad of the first die through flip-chip bonding, and wherein the third die and the fourth die have a gap therebetween;

forming a protection layer comprising vertical portions on sidewalls of the third and the fourth dies, and a horizontal portion directly over the first die and the second die; and

forming a coating on the protection layer and filling a remaining space of the space between the third and the fourth dies.

2. The method of claim 1, wherein the steps of providing the third and the fourth dies and stacking the third and the fourth dies comprise:

for each of the third and fourth dies, providing a substrate comprising an active device thereon;

forming an interconnect structure over the substrate;

forming the second bonding pad on the first surface and electrically coupled to the interconnect structure; and

forming through-silicon vias in the substrate.

3. The method of claim 2, wherein the steps of providing the third and the fourth dies and stacking the third and the fourth dies further comprise:

forming deep plugs extending from top surfaces of substrate into the substrate;

after the protection layer and the coating are formed, polishing the substrate to expose the deep plugs;

removing the deep plugs to form openings; and

performing the step of forming the through-silicon vias by filling the openings with a conductive material.

4. The method of claim 1 further comprising a sawing process to separate the first die and the third die from the second die and the fourth die, wherein the horizontal portion of the protection layer and the coating are sawed through, and wherein the vertical portions of the protection layer are not sawed.

5. The method of claim 1, wherein the step of forming the protection layer is performed using a method selected from the group consisting essentially of physical vapor deposition, dipping, plasma enhanced chemical vapor deposition (CVD), low pressure CVD, and atomic layer CVD.

6. The method of claim 1, wherein the step of forming the coating is performed using a method selected from the group consisting essentially of spin coating, stencil, and dipping.

7. The method of claim 1, wherein the horizontal portion and the vertical portions of the protection layer form a continuous layer with no break therebetween.

8. The method of claim 1, wherein the protection layer has a density greater than a density of the coating.

9. The method of claim 1 further comprising forming active devices at surfaces of the substrates of the first and the second dies, and forming interconnect structures over the substrates of the first and the second dies.

10. The method of claim 1, wherein the first and the third dies are stacked by forming a bond between the first bonding pad of the first die and the second bonding pad of the third die, wherein the bond is selected from the group consisting essentially of fusion bonding, diffusion bonding, and solder bonding.

11. A method comprising:

providing a wafer comprising a first die and a second die;

stacking a third die to the first die through flip-chip bonding, wherein a first gap is formed between the first die and the third die;

stacking a fourth die to the second die through flip-chip bonding, wherein a second gap is formed between the second die and the fourth die;

forming a protection layer on top surfaces of, and extending on sidewalls of, the third and the fourth dies, wherein the protection layer seals the first and the second gaps from aside;

filling a coating on the protection layer and filling an entirety of the space between the third and the fourth dies; and

performing a polish to remove portions of the protection layer directly over the top surfaces of the third and the fourth dies, until a top portion of each of the third and the fourth dies are removed.

12. The method of claim 11, wherein the third and fourth dies comprise dielectric vias in semiconductor substrates, and wherein after the step of performing the polish, the dielectric vias are exposed.

13. The method of claim 12 further comprising replacing the dielectric vias with through-silicon vias.

14. The method of claim 12, wherein the dielectric vias are embedded in the semiconductor substrates, with top layers of the semiconductor substrates covering the dielectric vias, and wherein in the step of performing the polish, the top layers of the semiconductor substrates are removed.

15. The method of claim 11, wherein during the step of stacking the third die to the first die, a bonding pad at a surface of the first die is bonded to a bonding pad at a surface of the third die through metal-to-metal bonding.

16. The method of claim 11, wherein the protection layer has a density greater than a density of the coating.

17. A method comprising:

providing a wafer comprising a first die and a second die, each comprising;

a first substrate; and

a first bonding over the first substrate;

forming a third die and a fourth die comprising;

providing a second substrate;

forming a deep dielectric plug in the second substrate;

forming an interconnect structure physically connected to the deep dielectric plug; and

forming a second bonding pad over, and electrically coupled to, the interconnect structure;

stacking the first die to the third die with the first bonding pad of the first die bonded to the second bonding pad of the third die;

stacking the second die to the fourth die with the first bonding pad of the second die bonded to the second bonding pad of the fourth die;

forming a protection layer, wherein the protection layer comprises vertical portions on sidewalls of the third and the fourth dies, and horizontal portions directly over the first and the second dies;

forming a coating on the protection layer and filling a remaining portion of the space horizontally between the third and the fourth dies;

polishing the coating, the protection layer, and the second substrates of the third and the fourth dies to expose the deep dielectric plugs;

replacing the deep dielectric plugs of the third and the fourth dies with a conductive material to form through-silicon vias; and

forming contact pads electrically coupled to the through-silicon vias.

18. The method of claim 17 further comprising a sawing process to separate the first die and the third die from the second die and the fourth die.

19. The method of claim 18 further comprising, before the step of sawing, stacking a fifth die on the third die, and forming an additional protection layer on a sidewall of the fifth die.