Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer
First Claim
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1. A method for manufacturing a trenched semiconductor power device comprising step of opening a trench in a semiconductor substrate and said method further comprising:
- forming an oxide layer on sidewalls and a bottom surface of said trench followed by filling said trench with a trenching filling material followed by an etch back process to remove from a top portion of said trench until a desired depth is reached;
depositing a high density plasma (HDP) oxide layer into said trench filling a space above said trench filling material and surrounded by said oxide layer on said trench sidewalls followed by an annealing densification process in an N2 or O2/N2 ambient environment at an elevated temperature for increasing an etch rate of said HDP oxide layer to be substantially the same as an etch rate of the oxide layer surrounding the HDP oxide layer; and
dry etching back said HDP oxide layer and partially etching the oxide layer on said trench sidewalls surrounding said HDP oxide layer to expose said HDP oxide layer followed by a dry or wet-etch to obtain a desired HDP oxide layer thickness and a desired oxide layer thickness of the oxide layer on said trench sidewalls.
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Abstract
This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
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Citations
10 Claims
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1. A method for manufacturing a trenched semiconductor power device comprising step of opening a trench in a semiconductor substrate and said method further comprising:
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forming an oxide layer on sidewalls and a bottom surface of said trench followed by filling said trench with a trenching filling material followed by an etch back process to remove from a top portion of said trench until a desired depth is reached; depositing a high density plasma (HDP) oxide layer into said trench filling a space above said trench filling material and surrounded by said oxide layer on said trench sidewalls followed by an annealing densification process in an N2 or O2/N2 ambient environment at an elevated temperature for increasing an etch rate of said HDP oxide layer to be substantially the same as an etch rate of the oxide layer surrounding the HDP oxide layer; and dry etching back said HDP oxide layer and partially etching the oxide layer on said trench sidewalls surrounding said HDP oxide layer to expose said HDP oxide layer followed by a dry or wet-etch to obtain a desired HDP oxide layer thickness and a desired oxide layer thickness of the oxide layer on said trench sidewalls. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for manufacturing a trenched semiconductor power device comprising step of opening a trench in a semiconductor substrate and said method further comprising:
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filling said trench with a trenching filling material followed by an etch back process to remove from a top portion of said trench until a desired depth is reached; depositing a high density plasma (HDP) oxide layer followed by an annealing densification process at an elevated temperature for increasing an etch rate of said HDP oxide layer to be substantially the same as an etch rate of a thermal oxide; and
whereinsaid step of filling said trench with a trench filling material further comprising a step of filling said trench with an un-doped polysilicon then doping said polysilicon with POCL3 followed by implanting phosphorous or boron ions.
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10. A method for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer separating a top and a bottom gate segments, the method further comprising:
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forming an oxide layer on sidewalls and a bottom surface of said trench followed by filling said trench with a trenching filling material followed by an etch back process to remove from a top portion of said trench until a desired depth is reached; forming said inter-poly layer by depositing a high density plasma (HDP) oxide layer into said trench filling a space above said trench filling material and surrounded by said oxide layer on said trench sidewalls followed by applying a RTP process in an N2 of O2/N2 ambient environment at an elevated temperature to bring an etch rate of the HDP oxide layer close to an etch rate of the oxide layer surrounding the HDP oxide layer; and dry etching back said HDP oxide layer and partially etching the oxide layer on said trench sidewalls surrounding said HDP oxide layer to expose said HDP oxide layer followed by a dry or wet-etch to obtain a desired HDP oxide layer thickness and a desired oxide layer thickness of the oxide layer on said trench sidewalls.
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Specification