Semiconductor device and fabrications thereof

• US 8,053,370 B2
• Filed: 01/08/2008
• Issued: 11/08/2011
• Est. Priority Date: 03/29/2007
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Yang, Wei-Tung, Liu, An-Hsiung
• Primary Examiner(s): Vinh; Lan
• Application Number:
  US11/971,001
• Publication Number:
  US 20080242100A1
• Time in Patent Office: 1,400 Days
• Field of Search: 438/424, 438/427, 438/706, 438/710, 438/736, 438/737, 438/738, 430/310, 430/312
• US Class Current: 438/736
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A method for forming a semiconductor device is disclosed. A substrate comprising a structural layer thereon is provided. A hard mask layer is formed on the structural layer. A photoresist layer is formed on the hard mask layer. The photoresist layer is patterned to from a plurality of main photoresist patterns and at least one dummy photoresist pattern between the main photoresist patterns or adjacent to one of the main photoresist patterns, wherein width of the dummy photoresist pattern is less than that of the main photoresist patterns. Two main photoresist patterns are separated with each other by a first opening, and two dummy photoresist patterns are separated with each other by a second opening. Width of the second opening is less than that of the first opening. The hard mask layer is patterned using the patterned photoresist layer as a mask. The structural layer is patterned using the patterned hard mask layer as a mask.

Claims

1. A method for forming a semiconductor device, comprising:

providing a substrate having a structural layer thereon;

forming a hard mask layer on the structural layer;

forming a photoresist layer on the hard mask layer;

patterning the photoresist layer to form multiple main photoresist patterns respectively separated from each other by a first width and multiple dummy photoresist patterns respectively separated from each other by a second width which is smaller than the first width, wherein a very dummy photoresist pattern is separated from the closest main photoresist pattern by one second width;

patterning the hard mask layer using the patterned photoresist layer as a mask to partially expose the hard mask layer to allow the exposed hard mask layer to have a shape corresponding to the main photoresist layer; and

patterning the structural layer using the patterned hard mask layer as a mask to partially expose the structural layer to allow the exposed structural layer to have a shape corresponding to the main photoresist layer;

wherein the second width is 50%-70% of that of the first width;

wherein the hard mask layer comprises a first hard mask layer formed on the structural layer and a second hard mask layer formed on the first hard mask layer;

wherein the second hard mask layer is etched to form multiple first openings respectively separated from each other by the first width, whereas the second hard mask layer is free of second openings respectively separated from each other by the second width.

2. The method as claimed in claim 1, wherein the first hard mask layer is silicon nitride, and the second hard mask layer is polysilicon.

3. The method as claimed in claim 1, wherein the first hard mask layer is silicon nitride, and the second hard mask layer is silicon oxide.

4. The method as claimed in claim 1, wherein the first hard mask layer is silicon nitride, and the second hard mask layer is carbide.

5. The method as claimed in claim 1, wherein the main photoresist patterns and the dummy photoresist patterns are strip shaped.

6. The method for forming a semiconductor device as claimed in claim 5, wherein the second width is 50%-70% of that of the first width.

7. A method for forming a semiconductor device, comprising:

providing a substrate having a structural layer thereon;

forming a first hard mask layer on the structural layer;

forming a second hard mask layer on the first hard mask layer;

forming a photoresist layer on the second hard mask layer;

patterning the photoresist layer to form multiple main photoresist patterns and first openings respectively separated from each other by a first width and dummy photoresist patterns and second openings respectively separated from each other by a second width which is smaller than the first width;

patterning the second hard mask layer to allow the second hard mask layer to have a shape corresponding only to that of the first openings;

removing the patterned photoresist layer;

patterning the first hard mask layer to allow the first hard mask to have a shape corresponding only to that of the first openings; and

patterning the structural layer so that the structural layer has a shape corresponding only to that of the first openings.

8. The method as claimed in claim 7, wherein the second width is of 50%-70% of that of the first width.

9. The method as claimed in claim 8, wherein the first hard mask layer is silicon nitride, and the second hard mask layer is polysilicon.

10. The method as claimed in claim 7, wherein the first hard mask layer is silicon nitride, and the second hard mask layer is silicon oxide.

11. The method for forming a semiconductor device as claimed in claim 10, wherein the first hard mask layer is silicon nitride, and the second hard mask layer is carbide.