Thin film transistor panel, method of fabricating the same, and organic light emitting display device including the same

• US 8,053,779 B2
• Filed: 04/05/2007
• Issued: 11/08/2011
• Est. Priority Date: 04/05/2006
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Im, Choong-Youl, Choi, Jong-Hyun, Kwon, Do-Hyun, Jun, Woo-Sik, Yoo, Kyung-Jin
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Garcia; Joannie A
• Application Number:
  US11/783,097
• Publication Number:
  US 20070238227A1
• Time in Patent Office: 1,678 Days
• Field of Search: 438/149, 438/151, 438/154, 438/155, 438/158, 438/164, 438/FOR.184, 438/FOR.201, 438/405, 438/455, 438/459, 438/974, 257/66, 257/67, 257/68, 257/69, 257/71, 257/202, 257/204, 257/E27.059, 257/E27.108, 257/E51.005, 257/E29.151, 257/E27.1, 257/E27.117, 257/E29.137, 257/E29.134, 257/E21.411, 148/DIG.12
• US Class Current: 257/71
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

Provided are a thin film transistor (TFT) panel, a method of fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT panel has a TFT region and a capacitor region. A TFT is formed in the TFT region and a capacitor is formed in the capacitor region. The TFT includes an active layer that includes a source and a drain regions. A gate insulation layer is formed on the active layer, and a gate electrode is formed on the gate insulation layer over the active layer. A source and a drain electrodes are formed over the active layer, and connected to the source and drain regions, respectively. In the TFT region, an interlayer insulation layer is formed between the gate electrode and the source/drain electrodes. In the capacitor region, an interlayer insulation layer is formed between a capacitor lower electrode and a capacitor upper electrode to form a capacitor. The interlayer insulation layers of the TFT region and the capacitor region have different layer structures and have different dielectric constants. Therefore, the capacitor region can have higher capacitance while the TFT region can have lower capacitance to reduce parasitic capacitance.

Claims

1. A thin film transistor panel comprising:

a substrate having a TFT region and a capacitor region on a surface of the substrate;

an active layer formed on the TFT region of the substrate, the active layer including a source region and a drain region;

a gate insulation layer formed on the TFT region and on the capacitor region of the substrate;

a gate electrode formed on the gate insulation layer over the active layer;

a TFT interlayer insulation layer formed in the TFT region, the TFT interlayer insulation layer formed on the gate electrode and on the TFT region;

a source electrode formed on the TFT interlayer insulation layer, the source electrode being connected to the source region;

a drain electrode formed on the TFT interlayer insulation layer, the drain electrode being connected to the drain region;

a capacitor lower electrode formed on the gate insulation layer of the capacitor region;

a capacitor interlayer insulation layer formed on the capacitor lower electrode, the capacitor interlayer insulation layer including a first capacitor insulation layer pattern formed on the capacitor lower electrode, the first capacitor insulation layer pattern not being formed on the gate electrode; and

a capacitor upper electrode formed on the capacitor interlayer insulation layer.

2. The thin film transistor panel according to claim 1, comprised of the capacitor interlayer insulation layer having a higher dielectric constant than the TFT interlayer insulation layer.

3. The thin film transistor panel according to claim 1, comprised of the capacitor interlayer insulation layer comprising:

a second capacitor insulation layer formed on the first capacitor insulation layer pattern.

4. The thin film transistor panel according to claim 3, comprised of the TFT interlayer insulating layer comprising:

a first TFT insulation layer pattern formed on a region of the gate insulation layer on which the gate electrode is not formed; and

a second TFT insulation layer formed on the first TFT insulation layer and formed on the gate electrode.

5. The thin film transistor panel according to claim 4, comprised of the first TFT insulation layer pattern being made of the same material as the first capacitor insulation layer pattern, and comprised of the second TFT insulation layer being made of the same material as the second capacitor insulation layer.

6. The thin film transistor panel according to claim 3, comprised of the TFT interlayer insulating layer comprising:

a first TFT insulation layer formed on the gate electrode and formed on the TFT region.

7. The thin film transistor panel according to claim 6, comprised of the first TFT insulation layer being made of the same material as the second capacitor insulation layer.

8. The thin film transistor panel according to claim 3, comprised of the first capacitor insulation layer pattern having a higher dielectric constant than the second capacitor insulation layer.

9. The thin film transistor panel according to claim 3, comprised of the first capacitor insulation layer pattern being made of a material selected from the group consisting of tantalum pentoxide (Ta₂O₅), titanium dioxide (TiO₂), silicon nitride (SiNx), and aluminum oxide (Al₂O₃).

10. The thin film transistor panel according to claim 3, comprised of the second capacitor insulation layer being made of a material selected from the group consisting of silicon oxide (SiO₂), silicon nitride (SiNx), and silicon oxynitride (SiON).

11. The thin film transistor panel according to claim 1, further comprising a passivation layer formed on the entire surface of the substrate having the source electrode, the drain electrode, and the capacitor upper electrode.

12. A method of fabricating a thin film transistor (TFT) panel, comprising:

preparing a substrate having a TFT region and a capacitor region on a surface of the substrate;

forming an active layer on the TFT region of the substrate, the active layer including a source region and a drain region;

forming a gate insulating layer on the TFT region and on the capacitor region of the substrate;

forming a gate electrode on the gate insulation layer over the active layer;

forming a capacitor lower electrode on the gate insulation layer of the capacitor region;

forming a capacitor interlayer insulation layer on the capacitor lower electrode, the capacitor interlayer insulation layer including a first insulation layer pattern formed on the electrode;

forming a second insulation layer to cover the gate electrode, the TFT region and the first insulation layer pattern, the second insulation layer formed on the gate electrode and the TFT region being a TFT interlayer insulation layer;

forming a source electrode on the TFT interlayer insulation layer formed in the TFT region, the source electrode being connected to the source region;

forming a drain electrode on the TFT interlayer insulation layer in the TFT region, the drain electrode being connected to the drain region; and

forming a capacitor upper electrode on the capacitor interlayer insulation layer formed in the capacitor region.

13. The method according to claim 12, comprised of the first insulation layer pattern having a higher dielectric constant than the second insulation layer.

14. An organic light emitting display device comprising:

a substrate having a TFT region and a capacitor region on a surface of the substrate;

an active layer formed on the TFT region of the substrate, the active layer including a source region and a drain region;

a gate insulation layer formed on the active layer and formed on the capacitor region of the substrate;

a gate electrode formed on the gate insulation layer over the active layer;

a TFT interlayer insulation layer formed in the TFT region, the TFT interlayer insulation layer formed on the gate electrode and formed on the TFT region;

a source electrode formed on the TFT interlayer insulation layer, the source electrode being connected to the source region;

a drain electrode formed on the TFT interlayer insulation layer, the drain electrode being connected to the drain region;

a capacitor lower electrode formed on the gate insulation layer of the capacitor region;

a capacitor interlayer insulation layer formed on the capacitor lower electrode, the capacitor interlayer insulation layer including a first capacitor insulation layer pattern formed on the capacitor lower electrode, the first capacitor insulation layer pattern not being formed on the gate electrode;

a capacitor upper electrode formed on the capacitor interlayer insulation layer;

a passivation layer formed on the entire surface of the substrate having the source electrode, the drain electrode, and the capacitor upper electrode; and

an organic light emitting diode having a first electrode, an organic layer, and a second electrode;

the first electrode of the organic light emitting diode being connected to the source electrode or the drain electrode.

15. The organic light emitting display device according to claim 14, comprised of the capacitor interlayer insulation layer having a higher dielectric constant than the TFT interlayer insulation layer.

16. The organic light emitting display device according to claim 14, comprised of the capacitor interlayer insulation layer comprising:

a second capacitor insulation layer formed on the first capacitor insulation layer pattern.

17. The organic light emitting display device according to claim 16, comprised of the TFT interlayer insulating layer comprising:

a first TFT insulation layer pattern formed on a region of the gate insulation layer on which the gate electrode is not formed; and

a second TFT insulation layer formed on the first capacitor insulation layer and formed on the gate electrode.

18. The organic light emitting display device according to claim 16, comprised of the first capacitor insulation layer having a higher dielectric constant than the second capacitor insulation layer.

19. The organic light emitting display device according to claim 17, comprised of the first insulation pattern being made of the same material as the first capacitor insulation layer pattern, and comprised of the second TFT layer being made of the same material as the second capacitor insulation layer.

20. The organic light emitting display device according to claim 16, comprised of the TFT interlayer insulating layer comprising:

a first TFT insulation layer formed on the gate electrode and formed on the TFT region.

21. The organic light emitting display device according to claim 20, comprised of the first TFT insulation layer being made of the same material as the second capacitor insulation layer.