Device including high-K metal gate finfet and resistive structure and method of forming thereof

• US 8,053,809 B2
• Filed: 05/26/2009
• Issued: 11/08/2011
• Est. Priority Date: 05/26/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Zhang, Ying
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): Wilson; Scott R
• Application Number:
  US12/471,872
• Publication Number:
  US 20100301417A1
• Time in Patent Office: 896 Days
• Field of Search: None
• US Class Current: 257/173
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A device is provided that in one embodiment includes a substrate having a first region and a second region, in which a semiconductor device is present on a dielectric layer in the first region of the substrate and a resistive structure is present on the dielectric layer in the second region of the substrate. The semiconductor device may include a semiconductor body and a gate structure, in which the gate structure includes a gate dielectric material present on the semiconducting body and a metal gate material present on the gate dielectric material. The resistive structure may include semiconductor material having a lower surface is in direct contact with the dielectric layer in the second region of the substrate. The resistive structure may be a semiconductor containing fuse or a polysilicon resistor. A method of forming the aforementioned device is also provided.

Claims

1. A device comprising:

a substrate comprising a first region and a second region in which a dielectric layer is present on the substrate;

a semiconductor device present on the dielectric layer in the first region of the substrate, the semiconductor device comprising a semiconducting body and a gate structure, the gate structure including a gate dielectric material present on the semiconducting body and a gate conductor material present on the gate dielectric material; and

a semiconductor containing fuse comprised of a layered structure including a conductive material atop a semiconductor material, the semiconductor containing fuse comprising an anode, a cathode, and a fuselink connecting the anode and the cathode, wherein the semiconductor material of the semiconductor containing fuse is in direct contact with the dielectric layer in the second region of the substrate.

2. The device of claim 1, wherein the gate dielectric material of the semiconductor device is not present between the semiconductor material of the semiconductor containing fuse and the dielectric layer in the second region of the substrate.

3. The device of claim 1, wherein the semiconductor device is a finFET and the semiconductor containing fuse is an eFuse.

4. The device of claim 1, wherein the semiconductor material of the semiconductor containing fuse comprises poly-silicon, amorphous silicon, epitaxial silicon, single crystal silicon, silicon germanium alloy, silicon carbon alloy, silicon carbon germanium alloy, a III-IV compound semiconductor, a II-VI compound semiconductor or a combination thereof.

5. The device of claim 1, wherein the conductive material of the semiconductor containing fuse comprises a metal, a metal nitride, a metal semiconductor alloy, or a combination thereof.

6. The device of claim 1, wherein the conductive material of the semiconductor containing fuse comprises nickel silicide, nickel platinum silicide, cobalt silicide, tantalum silicide, titanium silicide, Ta, Ti, W, Cu, Al, Ni, Ag, Au, tantalum nitride, titanium nitride, tungsten nitride or a combination thereof.

7. The device of claim 1, wherein the gate conductor material of the semiconductor device in the first region of the substrate is not present between the semiconductor layer of the semiconductor containing fuse and the dielectric layer in the second region of the substrate.

8. The device of claim 1, wherein the gate dielectric material comprises SiO₂, HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃ or a combination thereof.

9. The device of claim 1, wherein the gate dielectric material is a high-k dielectric.

10. The device of claim 1, wherein the gate conductor material comprises Ti, Zr, Hf, V, Nb, Ta, TiN, TaN or a combination thereof.

11. A device comprising:

a substrate comprising a first region and a second region, wherein a dielectric layer is present on the substrate;

a semiconductor device present on the dielectric layer in the first region of the substrate, the semiconductor device comprising a semiconductor body and a gate structure, the gate structure including a gate dielectric material present on the semiconducting body and a gate conductor material present on the gate dielectric material, wherein the gate dielectric material extends into the second region of the substrate; and

a semiconductor containing fuse comprised of a layered structure including a conductive material atop a semiconductor material, in which the layered structure includes an anode, a cathode, and a fuselink connecting the anode and the cathode, in which the gate dielectric material of the semiconductor device is present between and in direct contact with the semiconductor layer of the semiconductor containing fuse and the dielectric layer in the second region of the substrate.

12. A device comprising:

a substrate comprising a first region and a second region, wherein a dielectric layer is present on the substrate;

a semiconductor device present on the dielectric layer in the first region of the substrate, the semiconductor device comprising a semiconductor body and a gate structure, the gate structure including a gate dielectric material present on the semiconducting body and a gate conductor material present on the gate dielectric material; and

a semiconductor containing resistor comprised of a semiconductor material having a first terminal and a second terminal on an upper surface of the semiconductor material, the first terminal being separated from the second terminal so that the upper surface of the semiconductor material is exposed between the first terminal and the second terminal and so that current passing from the first terminal to the second terminal must pass through the semiconductor material that the first terminal and the second terminal is present on, wherein a lower surface of the semiconductor material of the resistive structure is in direct contact with the dielectric layer in the second region of the substrate.

13. The device of claim 12, wherein the gate conductor material of the semiconductor device in the first region of the substrate is not present between the semiconductor layer of the resistive structure and the dielectric layer in the second region of the substrate.

14. The device of claim 12, wherein the gate dielectric material is a high-k dielectric.

15. The device of claim 12, wherein the gate conductor material comprises Ti, Zr, Hf, V, Nb, Ta, TiN, TaN or a combination thereof.

16. A device comprising:

a substrate comprising a first region and a second region, wherein a dielectric layer is present on the substrate;

a semiconductor device present on the dielectric layer in the first region of the substrate, the semiconductor device comprising a semiconductor body and a gate structure, the gate structure including a gate dielectric material present on the semiconducting body and a gate conductor material present on the gate dielectric material, wherein the gate dielectric material of the semiconductor device extends into the second region of the substrate; and

a resistive structure comprised of a semiconductor material having a first terminal and a second terminal on an upper surface of the semiconductor material, wherein a lower surface of

the semiconductor material is in direct contact with the gate dielectric material of the semiconductor device that is present between and in direct contact with the semiconductor layer of the resistive structure and the dielectric layer in the second region of the substrate.

17. A method of forming a device comprising:

providing a substrate having a first region and second region, wherein the substrate comprises a dielectric surface;

forming a semiconductor body on the dielectric surface overlying the first region of the substrate;

forming a gate stack on the semiconductor body and overlying the dielectric surface in the first region and the second region of the substrate, wherein the gate stack includes a gate dielectric material in contact with at least the semiconductor body and the gate dielectric material is present on the dielectric surface of the second region of the substrate, and a gate conductor material on the gate dielectric material;

removing at least the gate conductor material from the gate stack in the second region of the substrate;

forming a semiconductor containing contact in electrical communication with the gate conductor material and a semiconductor component of a resistive structure in direct contact with the gate dielectric material that is overlying the dielectric surface of the second region of the substrate, wherein the semiconductor containing contact is separated from the semiconductor component of the resistive structure;

forming source and drain regions in the semiconductor body; and

forming a conductive structure to the semiconductor component of the resistive structure.

18. The method of claim 17, further comprising removing the gate dielectric material from the second region of the substrate, wherein the semiconductor component of the resistive structure is present in direct contact with the dielectric surface of the second region.

19. The method of claim 17, wherein the semiconductor body is configured to provide a finFET.

20. The method of claim 17, wherein the resistive structure is a polysilicon resistor, and the forming of the conductive structure to the semiconductor component comprises:

forming a first terminal on a first upper surface of the semiconductor component and a second terminal on a second upper surface of the semiconductor component; and

forming a first interconnect to the first terminal and a second interconnect to the second terminal.

21. The method of claim 17, wherein the resistive structure is a semiconductor containing fuse, and the forming of the conductive structure to the semiconductor component comprises:

forming a silicide layer over the semiconductor component, the silicide layer including a cathode, an anode, and a fuselink connecting the cathode to the anode; and

forming a first interconnect to the anode and a second interconnect to the cathode.