Contact in planar NROM technology

• US 8,053,812 B2
• Filed: 03/13/2006
• Issued: 11/08/2011
• Est. Priority Date: 03/17/2005
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Inventors: Shappir, Assaf
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): TRAN, TRANG Q
• Application Number:
  US11/373,932
• Publication Number:
  US 20060208281A1
• Time in Patent Office: 2,066 Days
• Field of Search: 257/202, 257/315, 257/410, 257/322, 257/324, 257/774, 257/E29.064
• US Class Current: 257/202
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for fabricating a non-volatile memory array includes placing contacts over bit lines in a self-aligned manner. The placing includes forming self-aligned contact holes bounded by a second insulating material resistant to the removal of a first insulating material previously deposited over the bit lines, and depositing contact material, wherein the second insulating material blocks effusion of the contact material beyond the contact holes. The distance between neighboring bit lines in the array does not include a margin for contact misalignment.

Claims

1. A non-volatile memory (“

NVM”

) device comprising;

a set of non-volatile memory cells disposed between and above two diffusion bit-lines, wherein at least one of the diffusion bit-lines is partially covered and in contact with a first insulator material and also partially covered and in contact with a second insulator material, wherein the first and second insulator materials are different;

an etched contact hole passing from a top surface of the first insulator material through to the at least one of the diffusion bit-lines, wherein the etched contact hole is formed by using an etching agent with which the second insulator material substantially does not react;

a first set of word-lines, wherein each of the word-lines in the first set is disposed across a group of adjacent cells; and

, a second set of word-lines parallel to the first set of word-lines, wherein there is spacing between the first and second sets of word-lines which does not include any word-lines, wherein the etched contact hole is located within the spacing between the first and second sets of word-lines.

2. The NVM device according to claim 1, wherein the second insulator material covers portions of the diffusion bit-line substantially at and around a border between said diffusion bit-line and a substrate of the device.

3. The NVM device according to claim 2, further comprising an electrically conducting contact to the diffusion bit-line in the etched contact hole, which contact is blocked from contacting the substrate by the second insulator material.