Chip capacitive coupling

• US 8,053,903 B2
• Filed: 02/24/2010
• Issued: 11/08/2011
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US12/711,793
• Publication Number:
  US 20100219503A1
• Time in Patent Office: 622 Days
• Field of Search: 257/777, 257/E25.006
• US Class Current: 257/777
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1358 being stacked
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 : Optical coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.

Claims

1. A semiconductor chip comprising:

semiconductor material including a first surface and a second surface opposite the first surface;

a first contact disposed on the first surface;

a via trench extending from the second surface of the semiconductor material into the semiconductor material; and

a conductive material disposed in the via trench;

wherein the conductive material and first contact are not directly electrically connected together but are configured to allow a signal to capacitively propagate between the conductive material and the first contact.

2. The semiconductor chip of claim 1, wherein at least a portion of the semiconductor material is disposed between the first contact and the conductive material.

3. The semiconductor chip of claim 1, wherein the semiconductor material is doped.

4. The semiconductor chip of claim 1, wherein a first portion of the semiconductor material comprises a substrate and a second portion of the semiconductor material comprises a doped semiconductor material, and wherein the first contact is disposed on one of the substrate or the doped semiconductor material and the via trench extends into the other of the substrate or the doped semiconductor material.

5. The semiconductor chip of claim 1, further comprising an electrically-insulative material disposed between the first contact and the conductive material such that the first contact is electrically insulated from the conductive material.

6. The semiconductor chip of claim 1, wherein the conductive material comprises a metallic stud.

7. The semiconductor chip of claim 1, wherein the conductive material comprises a coaxial conductor that includes a first conductor and a second conductor, and wherein the first and second conductors are electrically isolated from each other.

8. The semiconductor chip of claim 7, wherein at least a portion of the first conductor surrounds at least a portion of the second conductor.

9. The semiconductor chip of claim 1, wherein the conductive material comprises a triaxial conductor that includes a first conductor, a second conductor, and a third conductor that are electrically isolated from each other.

10. The semiconductor chip of claim 1, further comprising a second contact disposed on the first surface such that a second signal may capacitively propagate between the first contact and the second contact.

11. The semiconductor chip of claim 10, further comprising an insulator disposed between the first and second contacts such that the first and second contacts are electrically isolated from each other.

12. The semiconductor chip of claim 11, wherein the insulator comprises a photoresist or a tetraethylorthosilicate (TEOS) material.

13. The semiconductor chip of claim 1, further comprising an insulator disposed between the semiconductor material and the conductive material.

14. A semiconductor chip comprising:

a substrate including a first surface and a second surface opposite the first surface;

a first contact disposed along the first surface; and

a conductive material extending from the second surface into the substrate, wherein there is no direct electrical path between the first contact and the conductive material, and wherein the first contact and the conductive material are spaced apart by a distance configured to allow a signal to capacitively propagate between the first contact and the conductive material.

15. The semiconductor chip of claim 14, wherein at least a portion of the conductive material is disposed within a trench formed in the substrate.

16. The semiconductor chip of claim 14, wherein at least a portion of the substrate is disposed between the first contact and the conductive material.

17. The semiconductor chip of claim 14, wherein the substrate comprises a doped semiconductor material, and wherein the conductive material extends into the doped semiconductor material.

18. The semiconductor chip of claim 14, further comprising an electrically-insulative material disposed between the first contact and the conductive material such that the first contact is electrically insulated from the conductive material.

19. The semiconductor chip of claim 14, wherein the conductive material comprises a metallic stud.

20. The semiconductor chip of claim 14, wherein the conductive material comprises a coaxial conductor that includes a first conductor and a second conductor, and wherein the first and second conductors are electrically insulated from each other.

21. The semiconductor chip of claim 20, wherein the first conductor bounds an outer surface of the second conductor.

22. The semiconductor chip of claim 14, wherein the conductive material comprises a triaxial conductor that includes a first conductor, a second conductor, and a third conductor that are electrically insulated from each other.

23. The semiconductor chip of claim 14, further comprising a second contact disposed on the surface such that a second signal may capacitively propagate between the first contact and the second contact, wherein an insulator is disposed between the first contact and the second contact such that the first contact and the second contact are electrically insulated from each other.

24. A system comprising:

a first semiconductor chip including;

semiconductor material having a first side and a second side;

a first contact disposed on the first side;

a via trench extending from the second side into the semiconductor material; and

a conductive material disposed in the via trench, wherein the first contact and the conductive material are spaced apart by a distance configured to allow a signal to capacitively propagate between the first contact and the conductive material, and wherein there is no direct electrical connection between the first contact and the conductive material; and

a second semiconductor chip stacked on the first semiconductor chip, wherein the second semiconductor chip includes a second contact electrically connected to the conductive material.

25. The system of claim 24, wherein at least a portion of the semiconductor material is disposed between the first contact and the conductive material.

26. The system of claim 24, further comprising an electrically-insulative material disposed between the first contact and the conductive material such that the first contact is electrically insulated from the conductive material.

27. The system of claim 24, wherein the conductive material comprises a metallic stud.

28. The system of claim 24, wherein the conductive material comprises a coaxial conductor that includes a first conductor and a second conductor, and wherein the first and second conductors are electrically isolated from each other.

29. The system of claim 24, wherein the conductive material comprises a triaxial conductor that includes a first conductor, a second conductor, and a third conductor that are electrically isolated from each other.

30. The system of claim 24, wherein the second semiconductor chip comprises another conductive material spaced apart from the second contact by a distance configured to allow the signal to capacitively propagate between the second contact and the other conductive material, and wherein there is no direct electrical connection between the second contact and the other conductive material, the system further comprising a third semiconductor chip stacked on the second semiconductor chip, wherein the third semiconductor chip includes a third contact electrically connected to the other conductive material.