Integrated circuit operable in a standby mode

• US 8,054,120 B2
• Filed: 06/30/2009
• Issued: 11/08/2011
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics Application GmbH (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Application GmbH (STMicroelectronics NV)
• Inventors: Huber, Manfred, Heinrich, Peter
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US12/495,476
• Publication Number:
  US 20100327960A1
• Time in Patent Office: 861 Days
• Field of Search: None
• US Class Current: 327/198
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: Y10S 323/901 Starting circuits

Abstract

An integrated circuit, comprises a wakeup terminal; a supply voltage terminal configured to receive a supply voltage; and a power control circuit. The power control circuit comprises an enable circuit coupled to the wakeup terminal and configured to generate a voltage monitoring enable signal as a response to a wakeup signal received at the wakeup terminal, and a voltage monitoring circuit for generating a supply voltage level indication signal. The voltage monitoring circuit is coupled to the supply voltage terminal and comprises an operation switch controlled by the voltage monitoring enable signal. The voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and set the supply voltage level indication signal accordingly. The integrated circuit further comprises processing circuitry, with the supply voltage level indication signal controlling the switching between a normal operation state and a standby state of the processing circuitry.

Claims

1. An integrated circuit operable in a standby state, comprising:

a wakeup terminal configured to receive a wakeup signal;

a supply voltage terminal configured to be coupled to a supply voltage;

a power control circuit that includes;

an enable circuit coupled to the wakeup terminal and configured to receive the wakeup signal from the wakeup terminal and set a voltage monitoring enable signal as a response to the wakeup signal,

a voltage monitoring circuit coupled to the supply voltage terminal and including an operation switch configured to be controlled by the voltage monitoring enable signal, wherein the voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and to set a supply voltage level indication signal accordingly, and

an enable hold circuit configured to generate an enable hold signal and provide the enable hold signal to the enable circuit, wherein the enable circuit is further configured to set the voltage monitoring enable signal as a response to the enable hold signal; and

processing circuitry configured to process an input signal and to switch between a normal operation state and a standby state of the processing circuitry in response to the supply voltage level indication signal.

2. An integrated circuit according to claim 1, further comprising a plurality of terminals wherein the wakeup terminal is a subset of the plurality of terminals.

3. An integrated circuit according to claim 1, comprising at least one communication terminal coupled to the processing circuitry and configured to receive the input signal.

4. An integrated circuit according to claim 1, wherein the wakeup terminal is a communication terminal configured to receive at least part of the input signal.

5. An integrated circuit according to claim 1, wherein the enable hold circuit comprises a timer circuit coupled to the wakeup terminal, with the timer circuit being configured to be triggered by the wakeup signal received at the wakeup terminal and the enable hold circuit being configured to set the enable hold signal in response to a status of the timer circuit.

6. An integrated circuit according to claim 5, wherein the timer circuit is configured to be additionally triggered by the input signal.

7. An integrated circuit according to claim 1, wherein the enable hold circuit comprises an enable register, wherein the enable hold circuit is configured to set a content of the enable register in response to the input signal and process the content of the enable register to generate the enable hold signal.

8. An integrated circuit according to claim 7, wherein the enable hold circuit is configured to set the content of the enable register to a value indicating a standby command by processing a standby command signal of the input signal.

9. An integrated circuit according to claim 7, wherein the enable hold circuit comprises a timer circuit coupled to the enable register, with the timer circuit being configured to be triggered by the content of the enable register having a value indicating a standby command.

10. An integrated circuit according to claim 7, wherein the enable register is coupled to the voltage monitoring circuit, the voltage monitoring circuit being configured to supply the supply voltage level indication signal as a reset signal to the enable register.

11. An integrated circuit according to claim 1, wherein the enable hold circuit comprises:

a standby control circuit configured to generate a standby request signal; and

feedback circuitry configured to process the supply voltage level indication signal and the standby request signal in generating the enable hold signal.

12. An integrated circuit according to claim 11, wherein the standby control circuit is configured to generate the standby request signal as a response to at least one of the input signal and the wakeup signal.

13. An integrated circuit according to claim 11, wherein the standby control circuit comprises an enable register, the standby control circuit being configured to set a content of the enable register in response to the input signal and process the content of the enable register in generating the standby request signal.

14. An integrated circuit according to claim 13, wherein the standby control circuit further comprises a timer circuit coupled to the enable register.

15. An integrated circuit according to claim 11, wherein the standby control circuit comprises a timer circuit coupled to the at least one wakeup terminal.

16. An integrated circuit according to claim 1, wherein the enable circuit is a logic circuit.

17. An integrated circuit operable in a standby state, comprising:

a wakeup terminal configured to receive a wakeup signal;

a supply voltage terminal configured to be coupled to a supply voltage;

a power control circuit that includes;

an enable circuit coupled to the wakeup terminal and configured to receive the wakeup signal from the wakeup terminal and set a voltage monitoring enable signal as a response to the wakeup signal, and

a voltage monitoring circuit coupled to the supply voltage terminal and including an operation switch configured to be controlled by the voltage monitoring enable signal, wherein the voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and to set a supply voltage level indication signal accordingly;

processing circuitry configured to process an input signal and to switch between a normal operation state and a standby state of the processing circuitry in response to the supply voltage level indication signal; and

a plurality of output terminals configured to be coupled to electric components for providing power to the electric components, wherein the processing circuitry is configured to selectively provide power to the plurality of output terminals as a response to the input signal.

18. An integrated circuit according to claim 17, wherein the supply voltage terminal is configured to be coupled to a component power source having a component power source voltage as the supply voltage, the processing circuitry being configured to provide the component power source voltage to the electric components via the output terminals.

19. A system, comprising:

an electric component; and

an integrated circuit coupled to the electric component and operable in a standby state, the integrated circuit including;

at least one wakeup terminal;

a supply voltage terminal configured to be coupled to an external power source providing a supply voltage;

a power control circuit that includes;

an enable circuit coupled to the at least one wakeup terminal and configured to set a voltage monitoring enable signal as a response to a wakeup signal received at the at least one wakeup terminal,

a voltage monitoring circuit coupled to the supply voltage terminal and comprising an operation switch controlled by the voltage monitoring enable signal, wherein the voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and to set a supply voltage level indication signal accordingly, and

an enable hold circuit configured to generate an enable hold signal and provide the enable hold signal to the enable circuit, wherein the enable circuit is further configured to set the voltage monitoring enable signal as a response to the enable hold signal; and

processing circuitry configured to process an input signal, switch between a normal operation state and a standby state of the processing circuitry in response to the supply voltage level indication signal, and provide the electric component with power in the normal operation state.

20. The system of claim 19, wherein the enable hold circuit comprises a timer circuit coupled to the at least one wakeup terminal, with the timer circuit being configured to be triggered by the wakeup signal received at the at least one wakeup terminal and the enable hold circuit being configured to set the enable hold signal in response to a status of the timer circuit.

21. The system of claim 19, wherein the enable hold circuit comprises an enable register, wherein the enable hold circuit is configured to set a content of the enable register in response to the input signal and process the content of the enable register to generate the enable hold signal.

22. The system of claim 21, wherein the enable hold circuit further comprises a timer circuit coupled to the enable register, with the timer circuit being configured to be triggered by the content of the enable register having a value indicating a standby command.

23. The system of claim 21, wherein the enable register is coupled to the voltage monitoring circuit, the voltage monitoring circuit being configured to supply the supply voltage level indication signal as a reset signal to the enable register.

24. The system of claim 19, wherein the enable hold circuit comprises:

a standby control circuit configured to generate a standby request signal; and

feedback circuitry configured to process the supply voltage level indication signal and the standby request signal in generating the enable hold signal.

25. The system of claim 24, wherein the standby control circuit comprises an enable register, the standby control circuit being configured to set a content of the enable register in response to the input signal and process the content of the enable register in generating the standby request signal.

26. A system, comprising:

an electric component and

an integrated circuit coupled to the electric component and operable in a standby state, the integrated circuit including;

at least one wakeup terminal;

a supply voltage terminal configured to be coupled to an external power source providing a supply voltage;

a power control circuit that includes;

an enable circuit coupled to the at least one wakeup terminal and configured to set a voltage monitoring enable signal as a response to a wakeup signal received at the at least one wakeup terminal, and

a voltage monitoring circuit coupled to the supply voltage terminal and comprising an operation switch controlled by the voltage monitoring enable signal, wherein the voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and to set a supply voltage level indication signal accordingly;

processing circuitry configured to process an input signal, switch between a normal operation state and a standby state of the processing circuitry in response to the supply voltage level indication signal, and provide the electric component with power in the normal operation state; and

a plurality of output terminals coupled to the electric component for providing power to the electric component, wherein the processing circuitry is configured to selectively provide power to the plurality of output terminals as a response to the input signal.

27. The system of claim 26, wherein the power control circuit further includes an enable hold circuit configured to generate an enable hold signal and provide the enable hold signal to the enable circuit, wherein the enable circuit is further configured to set the voltage monitoring enable signal as a response to the enable hold signal.

28. A system, comprising:

an electric component of a group consisting of a lamp, an LED, and an electric motor; and

an integrated circuit coupled to the electric component and operable in a standby state, the integrated circuit including;

at least one wakeup terminal;

a supply voltage terminal configured to be coupled to an external power source providing a supply voltage;

a power control circuit that includes;

an enable circuit coupled to the at least one wakeup terminal and configured to set a voltage monitoring enable signal as a response to a wakeup signal received at the at least one wakeup terminal, and

a voltage monitoring circuit coupled to the supply voltage terminal and comprising an operation switch controlled by the voltage monitoring enable signal, wherein the voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and to set a supply voltage level indication signal accordingly; and

processing circuitry configured to process an input signal, switch between a normal operation state and a standby state of the processing circuitry in response to the supply voltage level indication signal, and provide the electric component with power in the normal operation state.

29. The system of claim 28, wherein the power control circuit further includes an enable hold circuit configured to generate an enable hold signal and provide the enable hold signal to the enable circuit, wherein the enable circuit is further configured to set the voltage monitoring enable signal as a response to the enable hold signal.