Limiter and semiconductor device using the same

• US 8,054,121 B2
• Filed: 02/26/2010
• Issued: 11/08/2011
• Est. Priority Date: 04/09/2004
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US12/713,723
• Publication Number:
  US 20100148845A1
• Time in Patent Office: 620 Days
• Field of Search: 327/309, 327/321, 327/312, 327/306, 257/360
• US Class Current: 327/309
• CPC Class Codes: G06K 19/07735 the record carrier comprising means for protecting against electrostatic discharge
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The limiter of the invention uses as a diode a stacked gate thin film transistor (TFT) including a floating gate. When the TFT including a floating gate is used, the threshold voltage Vth may be corrected by controlling the amount of charge accumulated in the floating gate even in the case where there are variations in the threshold voltages Vth of the TFT.

Claims

1. A semiconductor device comprising a limiter, the limiter including:

a transistor including a first gate and a second gate,

wherein a drain of the transistor is connected to the second gate;

wherein the drain and the second gate are connected to an input terminal for receiving an input voltage and an output terminal for providing a limit voltage;

wherein the first gate is capable of being in an electrically floating state; and

wherein the limiter is configured to change said limit voltage by controlling an amount of charge accumulated in the first gate by adjusting a gate voltage applied to said first gate and a source voltage applied to a source of the transistor.

2. The semiconductor device according to claim 1, further comprising a connecting terminal being connected to the drain of the transistor.

3. The semiconductor device according to claim 1, further comprising a connecting terminal being connected to said source of the transistor.

4. The semiconductor device according to claim 1, wherein the transistor is a thin film transistor.

5. The semiconductor device according to claim 1, further comprising a resistor, wherein the drain of the transistor is connected to the input terminal through the resistor.

6. A semiconductor device comprising a limiter, the limiter including:

at least two transistors, each including a first gate and a second gate,

wherein a drain and the second gate of each of the at least two transistors are connected to each other;

wherein the at least two transistors are connected in series so as to have the same forward current direction;

wherein the drain and the second gate of one of the at least two transistors are connected to an input terminal for receiving an input voltage and an output terminal for providing a limit voltage,

wherein the first gate of each of the at least two transistors is capable of being in an electrically floating state, and

wherein the limiter is configured to change said limit voltage by controlling an amount of charge accumulated in the first gates of the at least two transistors by adjusting a gate voltage applied to each said first gate and sources voltages applied to a source of each of the at least two transistors.

7. The semiconductor device according to claim 6, further comprising a connecting terminal being connected to anyone of the drain of the at least two transistors.

8. The semiconductor device according to claim 6, further comprising a connecting terminal being connected to any one of said sources of the at least two transistors.

9. The semiconductor device according to claim 6, wherein anyone of the at least two transistors is a thin film transistor.

10. The semiconductor device according to claim 6, further comprising a resistor, wherein the drain of one of the at least two transistors is connected to the input terminal through the resistor.

11. A semiconductor device comprising a limiter, the limiter including:

a first transistor including a first gate and a second gate; and

a second transistor;

wherein a drain and the second gate of the first transistor are connected to each other;

wherein a drain and a gate of the second transistor are connected to each other;

wherein the first transistor and the second transistor are connected in series so as to have the same forward current direction;

wherein the drain of the second transistor and the second gate are connected to an input terminal for receiving an input voltage and an output terminal for providing a limit voltage,

wherein the first gate of the first transistor is capable of being in an electrically floating state, and

wherein the limiter is configured to change said limit voltage by controlling an amount of charge accumulated in the first gate by adjusting a gate voltage applied to said first gate and a source voltage applied to a source of the first transistor.

12. The semiconductor device according to claim 11, further comprising a connecting terminal being connected to the drain of the first transistor.

13. The semiconductor device according to claim 11, further comprising a connecting terminal being connected to said source of the first transistor.

14. The semiconductor device according to claim 11, wherein the first transistor is a thin film transistor.

15. The semiconductor device according to claim 11, further comprising a resistor, wherein the drain of the second transistor and the second gate are connected to the input terminal through the resistor.

16. A semiconductor device comprising:

an integrated circuit, and

an antenna connected to the integrated circuit,

wherein the integrated circuit includes a limiter including a transistor, the transistor including a first gate and a second gate,

wherein a drain of the transistor is connected to the second gate;

wherein the drain and the second gate are connected to an input terminal for receiving an input voltage and an output terminal for providing a limit voltage;

wherein the first gate is capable of being in an electrically floating state; and

wherein the limiter is configured to change said limit voltage by controlling an amount of charge accumulated in the first gate by adjusting a gate voltage applied to said first gate and a source voltage applied to a source of the transistor.

17. The semiconductor device according to claim 16, further comprising a connecting terminal being connected to the drain of the transistor.

18. The semiconductor device according to claim 16, further comprising a connecting terminal being connected to said source of the transistor.

19. The semiconductor device according to claim 16, wherein the transistor is a thin film transistor.

20. The semiconductor device according to claim 16, further comprising a resistor, wherein the drain of the transistor is connected to the input terminal through the resistor.