Display device

• US 8,054,279 B2
• Filed: 09/11/2007
• Issued: 11/08/2011
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi, Miyake, Hiroyuki
• Primary Examiner(s): Mengistu; Amare
• Assistant Examiner(s): XAVIER, ANTONIO J
• Application Number:
  US11/853,090
• Publication Number:
  US 20080079685A1
• Time in Patent Office: 1,519 Days
• Field of Search: None
• US Class Current: 345/100
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2320/0646 Modulation of illumination source brightness and image signal correlated to each other
• CPC Class Codes: G09G 2320/0666 for control of colour parameters, e.g. colour temperature
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Claims

1. A display device comprising a pixel and a driver circuit, the driver circuit includes:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

wherein one of a source and a drain of the first transistor is directly connected to a fourth wiring, and the other of the source and the drain of the first transistor is electrically connected to a third wiring;

wherein one of a source and a drain of the second transistor is electrically connected to a seventh wiring, the other of the source and the drain of the second transistor is electrically connected to the third wiring, and a gate of the second transistor is electrically connected to a fifth wiring;

wherein one of a source and a drain of the third transistor is electrically connected to a sixth wiring, the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor, and a gate of the third transistor is directly connected to the fourth wiring;

wherein one of a source and a drain of the fourth transistor is electrically connected to the seventh wiring, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the sixth transistor, and a gate of the fourth transistor is electrically connected to the fifth wiring;

wherein one of a source and a drain of the fifth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor, and a gate of the fifth transistor is electrically connected to a first wiring;

wherein one of a source and a drain of the sixth transistor is electrically connected to the seventh wiring, and the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor;

wherein one of a source and a drain of the seventh transistor is electrically connected to the seventh wiring, the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring; and

wherein one of a source and a drain of the eighth transistor is electrically connected to the seventh wiring, the other of the source and the drain of the eighth transistor is electrically connected to the gate of the sixth transistor, and a gate of the eighth transistor is electrically connected to the gate of the first transistor.

2. The display device according to claim 1, wherein the first transistor has the largest value of W/L (a ratio of a channel width W to a channel length L) among the first to eighth transistors.

3. The display device according to claim 1, wherein the value of W/L (a ratio of a channel width W to a channel length L) of the first transistor is twice to five times a value of W/L of the fifth transistor.

4. The display device according to claim 1, wherein a channel width L of the third transistor is longer than a channel width L of the eighth transistor.

5. The display device according to claim 1, further comprising a capacitor configured to hold a voltage between the other of the source and the drain of the first transistor and the gate of the first transistor.

6. The display device according to claim 1, wherein the first to eighth transistors are N-channel transistors.

7. The display device according to claim 1, wherein the first to eighth transistors are formed by using amorphous silicon.

8. An electronic device comprising the display device according to claim 1.

9. The display device according to claim 1,

wherein the one of the source and the drain of the third transistor is directly connected to the sixth wiring, and

wherein the one of the source and the drain of the fifth transistor is directly connected to the sixth wiring.

10. The display device according to claim 1,

wherein the fourth wiring is supplied with a first clock signal,

wherein the fifth wiring is supplied with a second clock signal,

wherein the sixth wiring is supplied with a first potential, and

wherein the seventh wiring is supplied with a second potential.

11. A display device comprising a pixel, a first driver circuit, and a second driver circuit,

wherein the first driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

wherein one of a source and a drain of the first transistor is directly connected to a fourth wiring, and the other of the source and the drain of the first transistor is electrically connected to a third wiring;

wherein one of a source and a drain of the second transistor is electrically connected to a seventh wiring, the other of the source and the drain of the second transistor is electrically connected to the third wiring, and a gate of the second transistor is electrically connected to a fifth wiring;

wherein one of a source and a drain of the third transistor is electrically connected to a sixth wiring, the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor, and a gate of the third transistor is directly connected to the fourth wiring;

wherein one of a source and a drain of the fourth transistor is electrically connected to the seventh wiring, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the sixth transistor, and a gate of the fourth transistor is electrically connected to the fifth wiring;

wherein one of a source and a drain of the fifth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor, and a gate of the fifth transistor is electrically connected to a first wiring;

wherein one of a source and a drain of the sixth transistor is electrically connected to the seventh wiring, and the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor;

wherein one of a source and a drain of the seventh transistor is electrically connected to the seventh wiring, the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring;

wherein one of a source and a drain of the eighth transistor is electrically connected to the seventh wiring, the other of the source and the drain of the eighth transistor is electrically connected to the gate of the sixth transistor, and a gate of the eighth transistor is electrically connected to the gate of the first transistor;

wherein the second driver circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

wherein one of a source and a drain of the ninth transistor is electrically connected to an eleventh wiring, and the other of the source and the drain of the ninth transistor is electrically connected to a tenth wiring;

wherein one of a source and a drain of the tenth transistor is electrically connected to a fourteenth wiring, the other of the source and the drain of the tenth transistor is electrically connected to the tenth wiring, and a gate of the tenth transistor is electrically connected to a twelfth wiring;

wherein one of a source and a drain of the eleventh transistor is electrically connected to a thirteenth wiring, the other of the source and the drain of the eleventh transistor is electrically connected to a gate of the fourteenth transistor, and a gate of the eleventh transistor is electrically connected to the eleventh wiring;

wherein one of a source and a drain of the twelfth transistor is electrically connected to the fourteenth wiring, the other of the source and the drain of the twelfth transistor is electrically connected to the gate of the fourteenth transistor, and a gate of the twelfth transistor is electrically connected to the twelfth wiring;

wherein one of a source and a drain of the thirteenth transistor is electrically connected to the thirteenth wiring, the other of the source and the drain of the thirteenth transistor is electrically connected to a gate of the ninth transistor, and a gate of the thirteenth transistor is electrically connected to an eighth wiring;

wherein one of a source and a drain of the fourteenth transistor is electrically connected to the fourteenth wiring, and the other of the source and the drain of the fourteenth transistor is electrically connected to the gate of the ninth transistor;

wherein one of a source and a drain of the fifteenth transistor is electrically connected to the fourteenth wiring, the other of the source and the drain of the fifteenth transistor is electrically connected to the gate of the ninth transistor, and a gate of the fifteenth transistor is electrically connected to a ninth wiring; and

wherein one of a source and a drain of the sixteenth transistor is electrically connected to the fourteenth wiring, the other of the source and the drain of the sixteenth transistor is electrically connected to the gate of the fourteenth transistor, and a gate of the sixteenth transistor is electrically connected to the gate of the ninth transistor.

12. The display device according to claim 11, wherein the fourth wiring and the eleventh wiring are electrically connected, the fifth wiring and the twelfth wiring are electrically connected, the sixth wiring and the thirteenth wiring are electrically connected, and the seventh wiring and the fourteenth wiring are electrically connected.

13. The display device according to claim 12, wherein the fourth wiring and the eleventh wiring are the same wiring, the fifth wiring and the twelfth wiring are the same wiring, the sixth wiring and the thirteenth wiring are the same wiring, and the seventh wiring and the fourteenth wiring are the same wiring.

14. The display device according to claim 12, wherein the third wiring and the tenth wiring are electrically connected.

15. The display device according to claim 14, wherein the third wiring and the tenth wiring are the same wiring.

16. The display device according to claim 12, wherein the first transistor has the largest value of W/L (a ratio of a channel width W to a channel length L) among the first to eighth transistors, and the ninth transistor has the largest value of W/L among the ninth to sixteenth transistors.

17. The display device according to claim 12, wherein the value of W/L (a ratio of a channel width W to a channel length L) of the first transistor is twice to five times a value of W/L of the fifth transistor, and the value of W/L of the ninth transistor is twice to five times a value of W/L of the thirteenth transistor.

18. The display device according to claim 12, wherein a channel width L of the third transistor is longer than a channel width L of the eighth transistor, and wherein a channel width L of the eleventh transistor is longer than a channel width L of the sixteenth transistor.

19. The display device according to claim 12, further comprising a first capacitor configured to hold a voltage between the other of the source and the drain of the first transistor and the gate of the first transistor, and a second capacitor configured to hold a voltage between the other of the source and the drain of the ninth transistor and the gate of the ninth transistor.

20. The display device according to claim 12, wherein the first to sixteenth transistors are N-channel transistors.

21. The display device according to claim 12, wherein the first to sixteenth transistors use amorphous silicon as semiconductor layers.

22. An electronic device comprising the display device according to claim 11.

23. The display device according to claim 11,

wherein the one of the source and the drain of the third transistor is directly connected to the sixth wiring, and

wherein the one of the source and the drain of the fifth transistor is directly connected to the sixth wiring.

24. The display device according to claim 11,

wherein the fourth wiring is supplied with a first clock signal,

wherein the fifth wiring is supplied with a second clock signal,

wherein the sixth wiring is supplied with a first potential, and

wherein the seventh wiring is supplied with a second potential.