Increasing readout speed in CMOS APS sensors through block readout
First Claim
Patent Images
1. A CMOS active-pixel image sensor, comprising:
- a pixel array arranged in rows and columns comprising a plurality of pixels, each pixel comprising a photosensor and a source follower transistor; and
column selection circuitry connecting the pixel array to a master output bus and dividing the columns of the pixel array into a plurality of blocks, wherein the plurality of blocks comprises greater than 8 blocks and each of the plurality of blocks comprises a respective plurality of consecutive columns, the column selection circuitry comprising;
column output circuits connecting the columns in each block to a respective one of a plurality of block output lines;
block select switches connecting the block output lines to the master output bus; and
control circuitry connected to the block select switches operable to actively couple a single one of the blocks to the master output bus at a time.
2 Assignments
0 Petitions
Accused Products
Abstract
A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided with block signaling. Accordingly, only column output circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines. Block signaling allows increasing pixel readout rate while maintaining a constant frame rate for utility in large format high-speed imaging applications.
42 Citations
42 Claims
-
1. A CMOS active-pixel image sensor, comprising:
-
a pixel array arranged in rows and columns comprising a plurality of pixels, each pixel comprising a photosensor and a source follower transistor; and column selection circuitry connecting the pixel array to a master output bus and dividing the columns of the pixel array into a plurality of blocks, wherein the plurality of blocks comprises greater than 8 blocks and each of the plurality of blocks comprises a respective plurality of consecutive columns, the column selection circuitry comprising; column output circuits connecting the columns in each block to a respective one of a plurality of block output lines; block select switches connecting the block output lines to the master output bus; and control circuitry connected to the block select switches operable to actively couple a single one of the blocks to the master output bus at a time. - View Dependent Claims (2, 3)
-
-
4. A method comprising:
-
sampling a pixel in a selected row of a CMOS pixel array having pixels arranged in rows and columns; actively coupling a single one of a plurality of greater than two block output lines to an array readout bus at a time, each of the block output lines being coupled to a respective plurality of greater than two adjacent columns of the pixel array; and reading out a pixel value corresponding to the pixel in the selected row via the array readout bus, wherein reading out the pixel value comprises reading out a first value corresponding to the pixel value and reading out a second value corresponding to the pixel value. - View Dependent Claims (5, 6, 7)
-
-
8. A CMOS active pixel image sensor, comprising:
-
a pixel array comprising pixels including in-pixel buffer transistors, wherein the pixels are arranged in rows and columns and each of the pixels comprises a respective photosensor; column output lines, each of the column output lines coupled to at least one respective column of pixels of the array; first shared block lines; column output circuits to produce signals corresponding to pixel values generated by the pixels of the array, each of the column output circuits coupled to at least one respective column output line, wherein the column output circuits are arranged in blocks, and each of the blocks comprises a respective one of the first shared block lines coupled to a respective plurality of the column output circuits of a respective block; first column output select switches to enable first signals to be selectively transferred from the column output circuits to the first shared block lines, wherein each of the column output circuits comprises a respective one of the first column output select switches; a first shared readout line; and at least 8 first block select switches, each of the first block select switches coupled between a respective first shared block line of a respective block and the first shared readout line to enable the first signals to be selectively transferred from each respective first shared block line of each respective block to the first shared readout line, wherein only a single one of the first block select switches is to be activated at a time. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
-
-
26. An imaging device, comprising:
-
an array of pixels including a first set of adjacent columns of pixels coupled to a first set of column output circuits to provide a first set of signals, a second set of adjacent columns of pixels coupled to a second set of column output circuits to provide a second set of signals, and a third set of adjacent columns of pixels coupled to a third set of column output circuits to provide a third set of signals, wherein the first, second, and third sets of columns include the same number of columns and are adjacent to each other in the array, and the first, second, and third sets of signals are associated with a row of pixels in the array during a frame readout; and a first block select switch connected between the first set of column output circuits and a master output bus, a second block select switch connected between the second set of column output circuits and the output bus, and a third block select switch connected between the third set of column output circuits and the output bus, wherein the first, second, and third block select switches selectively provide only a single one of the first, second, and third sets of signals to the output bus at a time. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
-
Specification