Memory card using multi-level signaling and memory system having the same

• US 8,054,689 B2
• Filed: 06/18/2009
• Issued: 11/08/2011
• Est. Priority Date: 06/19/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Min-Soo, Heo, Seok-Won, Shin, Soong-Man, Lee, Chang-Duck
• Primary Examiner(s): NGUYEN, DANG T
• Application Number:
  US12/487,381
• Publication Number:
  US 20090316485A1
• Time in Patent Office: 873 Days
• Field of Search: 365/185.18, 365/189.09, 365/185.2, 365/189.11, 365/189.07, 365/185.03, 365/185.22, 365/189.16
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A memory card including a memory controller, a memory system and a method to control a memory are provided. The memory card includes a flash memory, a memory interface outputting a writing data signal to be written into the flash memory, and a multi-level converter transforming the writing data signal into a writing voltage signal to be provided to the flash memory. The writing voltage signal has one of different voltage levels in accordance with plural bits of the writing data signal.

Claims

1. A memory card comprising:

a flash memory;

a memory interface that outputs a first writing data signal to be written into the flash memory;

a first multi-level converter that generates a first writing voltage signal based on the first writing data signal, and outputs the first writing voltage signal to be provided to the flash memory,

wherein, to generate the first writing voltage signal, the first multi-level converter selects a voltage of the first writing voltage signal from a plurality of voltages in accordance with a plurality of bits of the first writing data signal;

a host interface that outputs a second reading data signal to be transferred to a host; and

a second multi-level converter that receives the second reading data signal, and generates a second reading voltage signal to be provided to the host based on the second reading data signal,

wherein a voltage of the second reading voltage signal is selected from the plurality of voltages in accordance with a plurality of bits of the second reading data signal, and

wherein the second multi-level converter receives a second writing voltage signal from the host, generates a second writing data signal in the unit of a plurality of bits based on the second writing voltage signal, and outputs the second writing data signal to be provided to the host interface.

2. The memory card of claim 1, wherein the multi-level converter receives a first reading voltage signal output from the flash memory, and generates a first reading data signal in a unit of plural bits based on the reading voltage signal which is provided to the memory interface.

3. The memory card of claim 1, further comprising a voltage generator that generates the plurality of voltages,

wherein the first multi-level converter comprises:

an encoder that encodes the first writing data signal in the unit of a plurality of bits to output an encoded signal;

a voltage selector that selects one of the plurality of voltages, corresponding to the encoded signal output from the encoder, as the first writing voltage signal, and provides the first writing voltage signal to the flash memory;

a voltage detector that detects a voltage of the first reading voltage signal; and

a decoder that generates the first reading data signal in the unit of a plurality of bits according to the detected voltage, to provide the first reading data signal to the memory interface.

4. The memory card of claim 3, wherein the unit of plurality of bits, in which the encoder encodes the first writing data signal, is n bits where n is equal to or greater than two (2), and

wherein the plurality of voltages generated from the voltage generator are 2ⁿ voltages.

5. The memory card of claim 3, wherein the detected voltage of the first reading voltage signal output from the flash memory corresponds to one of 2ⁿ voltage ranges where n is equal to or greater than two (2), each of the 2ⁿ ranges representing corresponding data having a plurality of bits.

6. The memory card of claim 1, wherein the flash memory comprises:

a memory circuit; and

a converter that receives the first writing voltage signal output from the first multi-level converter, generates a memory input data signal of a plurality of bits to be written to the memory circuit based on the first writing voltage signal, receives a memory output data signal read from the memory circuit, and generates the first reading voltage signal based on the memory output data signal which is to be provided to the multi-level converter,

wherein a voltage of the first reading voltage signal corresponds to one of 2ⁿ voltage ranges where n is equal to or greater than two (2), according to a plurality of bits of the memory output data signal, each of the 2ⁿ ranges representing corresponding data having a plurality of bits.

7. The memory card of claim 1, wherein the first multi-level converter receives a first reading voltage signal output from the flash memory, generates a first reading data signal in the unit of plural bits based on the first reading voltage signal, and outputs the first reading data signal to be provided to the memory interface.

8. The memory card of claim 1, wherein the second reading data signal is the first reading data signal which is output from the first multi-level converter and provided to the memory interface, and

wherein the second writing data signal is the first writing data signal which is output from the memory interface and provided to the first multi-level converter.

9. The memory card of claim 1, further comprising a voltage generator that generates the plural voltages,

wherein the first multi-level converter comprises:

a first encoder that encodes the first writing data signal in the unit of a plurality of bits to output a first encoded signal;

a first voltage selector that selects one of the plurality of voltages, corresponding to the first encoded signal output from the first encoder, as the first writing voltage signal, and provides the first writing voltage signal to the flash memory;

a first voltage detector that detects a voltage of the first reading voltage signal; and

a first decoder that generates the first reading data signal of the plurality of bits, according to the detected voltage, to provide the first reading data signal to the memory interface, and

wherein the second multi-level converter comprises;

a second encoder that encodes the second reading data signal in the unit of a plurality of bits to output a second encoded signal;

a second voltage selector that selects one of the plurality of voltages, corresponding to the second encoded signal output from the second encoder, as the second reading voltage signal to be provided to the host;

a second voltage detector that detects a voltage of the second writing voltage signal; and

a second decoder that generates the second writing data signal of the plurality of bits, according to the detected voltage, to provide the second writing data signal to the host interface.

10. The memory card of claim 1, wherein the flash memory comprises:

a memory circuit; and

a converter that receives the first writing voltage signal output from the first multi-level converter, generates a memory input data signal of a plurality of bits to be written to the memory circuit based on the first writing voltage signal, receives a memory output data signal read from the memory circuit, generates the first reading voltage signal based on the memory output data signal, and outputs the first reading voltage signal to be provided to the first multi-level converter,

wherein a voltage of the first reading voltage signal corresponds to one of 2ⁿ voltage ranges where n is equal to or greater than two (2), according to a plurality of bits of the memory output data signal, each of the 2ⁿ ranges representing corresponding data having a plurality of bits.

11. A memory system comprising:

a host; and

the memory connected to the host,

wherein the memory comprises;

a flash memory;

a memory interface that outputs a writing data signal to be written into the flash memory; and

a multi-level converter that generates a writing voltage signal based on the writing data signal, and outputs the writing voltage signal to be provided to the flash memory,

wherein, to generate the writing voltage signal, the multi-level converter selects a voltage of the writing voltage signal from a plurality of voltages in accordance with a plurality of bits of the writing data signal,

wherein the multi-level converter is a first multi-level converter, the writing data signal is a first writing data signal, the writing voltage signal is a first writing voltage signal,

wherein the memory card further comprises;

a host interface that outputs a second reading data signal to be transferred to a host; and

a second multi-level converter that receives the second reading data signal, and generates a second reading voltage signal to be provided to the host based on the second reading data signal,

wherein a voltage of the second reading voltage signal is selected from the plurality of voltages in accordance with a plurality of bits of the second reading data signal, and

wherein the host interface outputs the second reading data signal to be transferred to the host, and the second reading voltage signal is provided to the host.

12. The memory system of claim 11, wherein the host restores the second reading voltage signal from the second multi-level converter into a host input data signal of a plurality of bits to be provided to the host, outputs a host output data signal, generates the second writing voltage signal based on the host output data signal, and output the second writing voltage signal which is to be provided to the second multi-level converter,

wherein a voltage of the second writing voltage signal is selected from the plurality of voltages according to a plurality of bits of the host output data signal.

13. The memory system of claim 11, wherein two voltages of the plural voltages are supplied from the host to the voltage generator.

14. A method of controlling a flash memory using a host and a memory controller, the method comprising:

outputting a writing data signal to be written into the flash memory;

generating a writing voltage signal based on the writing data signal, and outputting the writing voltage signal to the flash memory;

receiving a reading voltage signal output from the flash memory;

generating a reading data signal based on the reading voltage signal, and outputting the reading data signal to the host,

wherein the writing voltage signal is selected from a plurality of voltages in accordance with plural bits of the writing data signal,

wherein the voltage of the reading voltage signal corresponds to one of 2ⁿ voltage ranges where n is equal to or greater than two (2), each of the 2ⁿ ranges representing corresponding data having plural bits, and

wherein the plurality of voltages do not include other than two voltages supplied from the host, and two voltages which are operational voltages of the flash memory.

15. The method of claim 14, wherein two voltages of the more than two voltages are supplied from the host to the voltage generator.

16. A memory card comprising:

a flash memory;

a voltage generator that generates a plurality of voltages;

a memory interface that outputs a writing data signal to be written into the flash memory, the writing data signal being input from a host; and

a multi-level converter that generates a writing voltage signal based on the writing data signal, and outputs the writing voltage signal to be provided to the flash memory,

wherein, to generate the writing voltage signal, the multi-level converter selects a voltage of the writing voltage signal from the plurality of voltages generated at the voltage generator in accordance with a plurality of bits of the writing data signal, and

wherein the plurality of voltages do not include other than two voltages supplied from the host, and two voltages which are operational voltages of the flash memory.