Self-referencing communication in implantable devices

• US 8,055,345 B2
• Filed: 08/29/2008
• Issued: 11/08/2011
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Original Assignee: Proteus Biomedical, Inc. (Otsuka Holdings Company Limited)
• Inventors: Li, Haifeng, Arne, Lawrence, Bi, Yafei, Zdeblick, Mark, Withrington, Jonathan, Jani, Nilay
• Primary Examiner(s): MANUEL, GEORGE C
• Application Number:
  US12/202,150
• Publication Number:
  US 20090062880A1
• Time in Patent Office: 1,166 Days
• Field of Search: 607/32
• US Class Current: 607/32
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/37288 Communication to several implantable medical devices within one patient

Abstract

Various aspects of the present invention enable robust, reliable control functionality for effectors present on intraluminal, e.g., vascular leads, as well as other types of implantable devices. Aspects of the invention include implantable integrated circuits that have self-referencing and self-clocking signal encoding, and are capable of bidirectional communication. Also provided by the invention are effector assemblies that include the integrated circuits, as well as implantable medical devices, e.g., pulse generators that include the same, as well as systems and kits thereof and methods of using the same, e.g., in pacing applications, including cardiac resynchronization therapy (CRT) applications.

Claims

1. An implantable integrated circuit, comprising:

(a) a first capacitor configured to be charged when a first phase control signal is asserted, said first phase control signal being related to a first predetermined phase of an encoded signal;

(b) a second capacitor configured to be charged when a second phase control signal is asserted, said second phase control signal being related to a second predetermined phase of said encoded signal; and

(c) a first comparator coupled to said first and second capacitors, said first comparator being configured to provide a first comparison result that indicates which of said first and second predetermined phases has a longer duration.

2. The implantable integrated circuit of claim 1, further comprising a second comparator configured to provide a second comparison result that indicates which of a third and a fourth predetermined phase of said encoded signal has a longer duration.

3. The implantable integrated circuit of claim 2, further comprising digital logic configured to receive said first and second comparison results and to determine a match to a symbol therefrom.

4. The implantable integrated circuit of claim 1, wherein said first and second phases are about 5 V, and said third and fourth phases are about 4.5 V.

5. The implantable integrated circuit of claim 1, wherein said encoded signal comprises a single wire interface to a controller.

6. A method for clock and data recovery in an implantable device, the method comprising:

(a) recovering a first clock from first and second high phases of an encoded signal, and a second clock from first and second low phases of said encoded signal;

(b) deriving first, second, third, and fourth phase control signals from said first and second recovered clocks;

(c) comparing pulse durations of said first and second phase control signal to generate a first comparison result, and comparing pulse durations of said third and fourth phase control signals to generate a second comparison result; and

(d) determining one of four symbols corresponding to said encoded signal using said first and second comparison results.

7. The method of claim 6, wherein said recovering said first and second clocks comprises translating said encoded signal into a full-swing signal.

8. The method of claim 6, wherein said comparing said pulse durations comprises charging capacitors for a time period corresponding to said phase control signal durations.

9. The method of claim 6, wherein said determining said one of four symbols comprises using digital logic that receives said first and second comparison results.

10. The method of claim 6, further comprising receiving said encoded signal from a controller on a single wire interface.

11. The method of claim 6, further comprising receiving a wakeup indication to enable said recovering.

12. A computer-readable storage device, comprising:

(a) one or more instructions for recovering a first clock from first and second high phases of an encoded signal, and a second clock from first and second low phases of said encoded signal;

(b) one or more instructions for deriving first, second, third, and fourth phase control signals from said first and second recovered clocks;

(c) one or more instructions for comparing pulse durations of said first and second phase control signal to generate a first comparison result, and comparing pulse durations of said third and fourth phase control signals to generate a second comparison result; and

(d) one or more instructions for determining one of four symbols corresponding to said encoded signal using said first and second comparison results.

13. The computer-readable storage device of claim 12, wherein said recovering said first and second clocks comprises one or more instructions for translating said encoded signal into a full-swing signal.

14. The computer-readable storage device of claim 12, wherein said comparing said pulse durations comprises one or more instructions for charging capacitors for a time period corresponding to said phase control signal durations.

15. The computer-readable storage device of claim 12, wherein said determining said one of four symbols comprises one or more instructions for using digital logic that receives said first and second comparison results.

16. The computer-readable storage device of claim 12, further comprising one or more instructions for receiving said encoded signal from a controller on a single wire interface.

17. The computer-readable storage device of claim 12, further comprising one or more instructions for receiving a wakeup indication to enable said recovering.

18. An implantable controller having an interface configured to communicate to an implantable satellite device, said interface comprising:

(a) a ground terminal; and

(b) a signal terminal configured to transmit an encoded signal to said implantable satellite device, wherein said encoded signal comprises first and second high phases and first and second low phases.

19. The implantable controller of claim 18, wherein said encoded signal comprises said first high phase, followed by said first low phase, followed by said second high phase, followed by said second low phase.

20. The implantable controller of claim 18, wherein said encoded signal comprises one of four symbols.

21. The implantable controller of claim 18, wherein said encoded signal comprises about a 500 mV variation over a nominal 5 V signal.

22. The implantable controller of claim 18, wherein said ground terminal is configured to be coupled to a human body.