Memory controllers, memory systems, solid state drives and methods for processing a number of commands

• US 8,055,816 B2
• Filed: 04/09/2009
• Issued: 11/08/2011
• Est. Priority Date: 04/09/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi, Yang, Jui-Yao (Ray), Liao, Yu-Song, Nemazie, Siamack
• Primary Examiner(s): Hafiz; Tariq
• Assistant Examiner(s): SUN, SCOTT C
• Application Number:
  US12/421,093
• Publication Number:
  US 20100262721A1
• Time in Patent Office: 943 Days
• Field of Search: None
• US Class Current: 710/39
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Claims

1. A memory controller, comprising:

a plurality of back end channels, each back end channel corresponding to a different memory device;

a command queue communicatively coupled to the plurality of back end channels, the command queue being configured to hold host commands communicated by a host; and

circuitry configured to;

generate a number of back end commands at least in response to a number of the host commands in the command queue, wherein the number of back end commands is different than the number of the host commands, and

distribute the number of back end commands to a number of the plurality of back end channels, wherein the number of back end commands is at least equal to the number of back end channels.

2. The memory controller of claim 1, wherein the number of back end commands is fewer than the number of the host commands.

3. The memory controller of claim 1, wherein the number of back end commands is greater than the number of the host commands.

4. The memory controller of claim 3, wherein the circuitry is configured to:

generate a respective back end command corresponding to each of the plurality of back end channels in response to a single host command, and

distribute the respective back end command to its corresponding back end channel, such that the back end commands are processed substantially in parallel.

5. The memory controller of claim 4, wherein the circuitry is configured to communicate results to the host from executing a particular one of the multiple back end commands upon completion of the particular one of the multiple back end commands, without regard to completion of execution of any other of the multiple back end commands.

6. The memory controller of claim 1, wherein the circuitry is configured to distribute multiple host commands among different multiple back end channels such that the multiple host commands are executed substantially simultaneously by the multiple back end channels.

7. The memory controller of claim 1, wherein generating the number of back end commands includes the combination of modifying at least one of the number of host commands and deleting at least another one of the number of host commands.

8. The memory controller of claim 1, wherein a Direct Memory Access module (DMA) is configured to distribute data associated with a host command corresponding to the number of back end commands generated.

9. The memory controller of claim 1, wherein the circuitry is a command dispatcher having a command processor portion configured to modify host commands so as to optimize distribution of the commands among the plurality of back end channels, and a dispatcher portion configured to distribute the modified commands among the plurality of back end channels.

10. The memory controller of claim 1, wherein the circuitry is a front end processor (FEP) communicatively coupled to the plurality of back end channels, the FEP being configured to modify host commands so as to optimize distribution of the commands among the plurality of back end channels.