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Memory controllers, memory systems, solid state drives and methods for processing a number of commands

  • US 8,055,816 B2
  • Filed: 04/09/2009
  • Issued: 11/08/2011
  • Est. Priority Date: 04/09/2009
  • Status: Active Grant
First Claim
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1. A memory controller, comprising:

  • a plurality of back end channels, each back end channel corresponding to a different memory device;

    a command queue communicatively coupled to the plurality of back end channels, the command queue being configured to hold host commands communicated by a host; and

    circuitry configured to;

    generate a number of back end commands at least in response to a number of the host commands in the command queue, wherein the number of back end commands is different than the number of the host commands, anddistribute the number of back end commands to a number of the plurality of back end channels, wherein the number of back end commands is at least equal to the number of back end channels.

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