System and method for increasing capacity, performance, and flexibility of flash storage

• US 8,055,833 B2
• Filed: 12/15/2006
• Issued: 11/08/2011
• Est. Priority Date: 10/05/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Smith, Michael J. S., Rajan, Suresh, Danilak, Radoslav
• Primary Examiner(s): PEUGH, BRIAN R
• Application Number:
  US11/611,374
• Publication Number:
  US 20080086588A1
• Time in Patent Office: 1,789 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.

Claims

1. An interlace circuit configured to couple to one or more flash memory devices, comprising:

a read-only memory (ROM) storing fixed configuration information associated with the one or more flash memory devices;

discovery topic circuitry configured to;

detect a physical configuration for the one or more flash memory devices, and

determine a virtual configuration for the one or more flash memory devices based on, at least in part, the physical configuration and based on, at least in part, the fixed configuration information stored in the ROM;

configuration logic circuitry configured to store the virtual configuration for one or more virtual flash memory devices; and

a translation unit configured to;

receive a request from a host system to access at least one of the one or more flash memory devices, wherein information associated with the request is based on the virtual configuration for the one or more virtual flash memory devices, and

translate the request received from the host system to a translated request that includes information associated with the physical configuration for the one or more flash memory devices.

2. The interface circuit as recited in claim 1, wherein the one or more virtual flash memory devices comprise a capacity greater than any one of the one or more flash memory devices.

3. The interface circuit as recited in claim 1, wherein the one or mare virtual flash memory devices comprise a capacity equal to a sum of the capacities of the one or more flash memory devices.

4. The interface circuit as recited in claim 1, wherein the discovery logic is further configured to compute one or more parameters of the virtual flash memory device.

5. The interface circuit as recited in claim 4, wherein the one or more parameters are reported to the host system.

6. The interface circuit as recited in claim 1, wherein the translation unit is configured to translate a protocol implemented by the host system to a protocol implemented by the one or more flash memory devices.

7. The interface circuit as recited in claim 1, wherein, if a block of data locations in the one or more virtual flash memory devices is detected to be bad, then the interface circuit is configured to remap addresses in the block from a first set of storage locations in the one or more flash memory devices to a second set of storage locations in the one or more flash memory devices.

8. The interface circuit as recited in claim 1, wherein the interface circuit is configured to generate an erasure operation independent of a write operation.

9. The interface circuit as recited in claim 8, wherein the erasure operation erases a block in one of the one or more flash memory devices, wherein the block has been marked as garbage for garbage collection.

10. The interface circuit as recited in claim 8, wherein the erasure operation is generated by the interface circuit to pre-erase unused blocks in the one or more flash memory devices.

11. The interface circuit as recited in claim 1, further comprising one or more buffers configured to store write operations provided from the host system, wherein the interface circuit is configured to report that an erasure operation corresponding to a write operation has completed prior to actual completion of the erasure operation, and wherein the interface circuit is configured to store the write operation in the buffer until the erasure operation is actually complete.

12. The interface circuit as recited in claim 1, wherein the discovery logic circuitry is further configured to discover attributes of the one or more flash memory devices.

13. An apparatus comprising:

one or more flash memory devices; and

an interface circuit, including;

a read-only memory (ROM) storing fixed configuration information associated with the one or more flash memory devices;

discovery logic circuitry configured to;

detect a physical configuration for the one or more flash memory devices, and

determine a virtual configuration for the one or more flash memory devices based on, at least in part, the physical configuration and based on, at least in part, the fixed configuration information stored in the ROM, and

configuration logic circuitry configured to store the virtual configuration for one or more virtual flash memory devices,

wherein the interface circuit is coupled to a host system,

wherein the interface circuit is configured to present a standard interface to the host system and is configured to provide another interface to the one or more flash memory devices that differs from the standard interface, wherein the standard interface is associated with the physical configuration and the another interface is associated with the virtual configuration.

14. The apparatus as recited in claim 13 wherein the standard interface is pin-compatible with a previous generation of flash memory devices.

15. The apparatus as recited in claim 13 wherein the interface circuit and the one or more flash memory devices are stacked.

16. The apparatus as recited in claim 13 wherein the one or more flash memory devices and the interface circuit are integrated onto a single semiconductor substrate.

17. An apparatus comprising:

one or more flash memory devices;

a flash memory controller; and

an interface circuit including;

a read-only memory (ROM) storing fixed configuration information associated with the one or more flash memory devices,

discovery logic circuitry configured to;

detect a physical configuration for the one or more flash memory devices, and

determine a virtual configuration for the one or more flash memory devices based on, at least in part, the physical configuration and based on, at least in part, the fixed configuration information stored in the ROM,

configuration logic circuitry configured to store the virtual configuration for one or more virtual flash memory devices, and

a translation unit configured to;

receive a request from the flash memory controller to access at least one of the one or more flash memory devices, wherein information associated with the request is based on the virtual configuration for the one or more virtual flash memory device, and

translate the request received from the flash memory controller to a translated request that includes information associated with the physical configuration for the one or more flash memory devices.

18. The apparatus as recited in claim 17, wherein the translation unit is further configured to translate a protocol implemented by the flash memory controller to a protocol implemented by the one or more flash memory devices, and wherein the translation unit is further configured to translate the protocol implemented by the one or more flash memory devices to the protocol implemented by the flash memory controller.

19. The apparatus as recited in claim 17 wherein the protocol implemented by the flash memory controller is one of a NAND protocol or a NOR protocol and the protocol implemented by the flash memory controller is the other one of the NAND protocol and the NOR protocol.