Translated memory protection apparatus for an advanced microprocessor

• US 8,055,877 B1
• Filed: 10/11/2005
• Issued: 11/08/2011
• Est. Priority Date: 08/22/1996
• Status: Expired due to Term

• Current Assignee: Liberty Patents LLC
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Wing, Malcolm J., Cmelik, Robert F., Kelly, Edmund J.
• Primary Examiner(s): Thai; Tuan V.
• Application Number:
  US11/248,813
• Time in Patent Office: 2,219 Days
• Field of Search: 711/100, 711/147, 711/154, 711/200, 711/202, 711/203, 711/206, 711/207, 714/9, 714/53, 714/723
• US Class Current: 711/206
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 9/3808 for instruction reuse, e.g. trace cache, branch target cache
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Abstract

A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Claims

1. A processor, comprising:

a translator configured to translate target instructions of a target program into host instructions;

an execution pipeline configured to execute the host instructions, wherein at least one of the host instructions are executed speculatively; and

a memory cache configured to hold the host instructions, wherein the execution pipeline includes a configuration to re-executed host instructions held in the memory cache without translating the corresponding target instruction of the program to the host instructions held in the memory cache again.

2. The processor of claim 1, wherein one of the host instructions is executed out of target program order.

3. The processor of claim 1, wherein the memory cache is a translation buffer.

4. The processor of claim 3, wherein one of the host instructions is executed out of target program order.

5. A processor, comprising:

a translator configured to translate target instructions of a program into host operations;

a memory buffer coupled to the translator and configured to store the host operations wherein the stored host operations can be fetched, issued and re-executed later from the memory buffer without translating the corresponding target instruction of the program to the stored host operation held in the memory buffer again;

a fetch pipeline stage coupled to the memory buffer and configured to fetch the host operations;

an issue pipeline stage configured to issue host operations; and

multiple execution units coupled to the issue pipeline stage and configured to execute host operations.

6. The processor of claim 5, wherein one of the host operations is executed speculatively.

7. The processor of claim 6, wherein the target instructions are compliant with the x-86 instruction set.

8. The processor of claim 6, wherein the speculatively executed host operation is a memory store operation.

9. The processor of claim 8, wherein the target instructions are compliant with the x-86 instruction set.

10. The processor of claim 6, wherein the speculatively executed host operation is a conditional branch operation.

11. The processor of claim 10, wherein the target instructions are compliant with the x-86 instruction set.

12. A method of operating a processor, comprising:

translating target instructions of a target program into host instructions;

executing the host instructions in an execution pipeline, wherein at least one of the host instructions are executed speculatively; and

holding the host instructions in a memory cache for subsequent execution without translating the corresponding target instruction of the program to the host instruction held in the memory cache again.

13. The method of claim 12, wherein one of the host instructions is executed out of target program order.

14. The method of claim 12, further comprising executing host instructions retrieved from the memory cache in response to an exception.

15. A processor, comprising:

a means for translating instructions of a program into host operations;

a means for executing the host operations; and

a means for caching the host operations wherein the cached host operations are re-executed without translating the corresponding instruction of the program again.

16. The processor of claim 15, wherein the instructions of the program are compliant with the x-86 instruction set.

17. The processor of claim 15, further comprising the means for executing the host operations wherein at least one host operation is executed speculatively.

18. The processor of claim 17, wherein a speculatively executed host operation is a memory operation.

19. The processor of claim 17, wherein a speculatively executed host operation is a condition branch operation.

20. The processor of claim 15, wherein the cached host operations are executed in response to an exception.