Translated memory protection apparatus for an advanced microprocessor
First Claim
Patent Images
1. A processor, comprising:
- a translator configured to translate target instructions of a target program into host instructions;
an execution pipeline configured to execute the host instructions, wherein at least one of the host instructions are executed speculatively; and
a memory cache configured to hold the host instructions, wherein the execution pipeline includes a configuration to re-executed host instructions held in the memory cache without translating the corresponding target instruction of the program to the host instructions held in the memory cache again.
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Abstract
A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
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Citations
20 Claims
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1. A processor, comprising:
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a translator configured to translate target instructions of a target program into host instructions; an execution pipeline configured to execute the host instructions, wherein at least one of the host instructions are executed speculatively; and a memory cache configured to hold the host instructions, wherein the execution pipeline includes a configuration to re-executed host instructions held in the memory cache without translating the corresponding target instruction of the program to the host instructions held in the memory cache again. - View Dependent Claims (2, 3, 4)
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5. A processor, comprising:
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a translator configured to translate target instructions of a program into host operations; a memory buffer coupled to the translator and configured to store the host operations wherein the stored host operations can be fetched, issued and re-executed later from the memory buffer without translating the corresponding target instruction of the program to the stored host operation held in the memory buffer again; a fetch pipeline stage coupled to the memory buffer and configured to fetch the host operations; an issue pipeline stage configured to issue host operations; and multiple execution units coupled to the issue pipeline stage and configured to execute host operations. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. A method of operating a processor, comprising:
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translating target instructions of a target program into host instructions; executing the host instructions in an execution pipeline, wherein at least one of the host instructions are executed speculatively; and holding the host instructions in a memory cache for subsequent execution without translating the corresponding target instruction of the program to the host instruction held in the memory cache again. - View Dependent Claims (13, 14)
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15. A processor, comprising:
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a means for translating instructions of a program into host operations; a means for executing the host operations; and a means for caching the host operations wherein the cached host operations are re-executed without translating the corresponding instruction of the program again. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification