Reconfigurable circuit having a pipeline structure for carrying out time division multiple processing

• US 8,055,880 B2
• Filed: 02/09/2005
• Issued: 11/08/2011
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ishihara, Teruo, Yosizawa, Hideki, Fujisawa, Hisanori
• Primary Examiner(s): HUISMAN, DAVID J
• Application Number:
  US11/053,269
• Publication Number:
  US 20060004992A1
• Time in Patent Office: 2,463 Days
• Field of Search: 712/10, 712/11, 712/15, 326/38, 326/39
• US Class Current: 712/15
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

The reconfigurable circuit of the present invention in which time division multiple processing is possible has a pipeline structure with the number of stages of an integral multiple of a given number, and comprises a plurality of processor elements having a processing unit whose configuration is variable according to first configuration data to be supplied, a network in which all inputs and outputs of a plurality of said processor elements are connected and which transfers data by one clock between the input and output according to second configuration data to be supplied, and a switching unit which cyclically switches by one clock and supplies the first and second configuration data prepared for the given number of tasks to each of the processing units.

Claims

1. A reconfigurable circuit for time division multiple processing, and wherein a given number of tasks are processed in parallel, comprising:

a plurality of processor elements, each processor element having a pipeline structure and at least one processing unit in which configurations are changeable according to first configuration data to be supplied;

a network in which the inputs and outputs of the plurality of processor elements are connected and which transfers data between the inputs and outputs according to second configuration data to be supplied;

a switching unit that switches the first and second configuration data prepared for the given number of tasks in a predetermined order at a predetermined rate, outputs the switched first and second configuration data to each processing unit, and in one clock cycle of a first clock signal alternatively switches and outputs the first and second configuration data and supplies the alternatively switched first and second configuration data so that the alternatively switched first and second configuration data synchronizes with a periodic signal at each pipeline structure of the processor elements; and

a parallel/serial conversion unit for forwarding a number of inputs equal to the given number of tasks to the network in synchronization with the first clock signal;

wherein the switching unit processes a task for each processing unit of each one of the processor elements with a time lag;

wherein the switching unit generates configuration data into which configuration data of a different task is integrated;

wherein the switching unit comprises;

a storage unit for storing the first and second configuration data for every task;

an output position designation unit which forms a pair with the storage unit and designates the position of data to be outputted from the storage unit; and

a task switching unit for switching the output of the storage unit according to the task to be processed; and

wherein the parallel/serial conversion unit comprises;

a number of latches corresponding to the given number of tasks for holding the number of inputs in synchronization with the first clock signal;

a counter for counting clock cycles of a second clock signal with which each processing unit of each one of the processor elements operates, a frequency of the second clock signal being a frequency of the first clock signal multiplied by the given number; and

a selector for selecting and outputting one of the inputs held in the latches in accordance with an output of the counter.

2. The reconfigurable circuit according to claim 1, comprising:

a parallel/serial conversion unit for outputting time division multiplex data supplied from the network to a given number of output terminals.

3. The reconfigurable circuit according to claim 2, further comprising:

a timing adjustment unit for adjusting the timing of the outputted time division multiplex data in order to enable an output of the serial/parallel conversion unit to be connected to the given number of inputs of the parallel/serial conversion unit, and

wherein the serial/parallel conversion unit outputs processing data from the tasks in a predetermined order to the processor elements.

4. The reconfigurable circuit according to claim 1, further comprising:

a correlation transfer unit for transferring data between different configuration phases.

5. The reconfigurable circuit according to claim 4, wherein

the correlation transfer unit comprises a selector in which the output of a processing unit of a transfer source is an input of the correlation transfer unit, and an output of the correlation transfer unit is connected to a desired transfer destination.

6. The reconfigurable circuit according to claim 5, wherein

the desired transfer destination is one of the number of latches of the parallel/serial converting unit.

7. The reconfigurable circuit according to claim 1, wherein

the pipeline structure has a number of stages of an integral multiple of the given number of tasks.

8. The reconfigurable circuit according to claim 7, further comprising:

a delay unit in at least one processing unit of each processor element in order to set configurations by replacing each configuration with a configuration of the next pipeline stage with a one clock cycle delay.

9. The reconfigurable circuit according to claim 1, comprising:

a pipeline configuration for enhancing throughput via flip-flops so that the number of pipeline structures increases.

10. A reconfigurable circuit for time division multiple processing, and wherein a given number of tasks are processed in parallel, comprising:

a plurality of processor elements, each processor element having a pipeline structure and at least one processing unit in which configurations are changeable according to first configuration data to be supplied;

a network in which inputs and outputs of the plurality of processor elements are connected and which transfers data between the inputs and outputs according to second configuration data to be supplied;

a switching unit that switches the first and second configuration data prepared for the given number of tasks in a predetermined order at a predetermined rate, outputs the switched first and second configuration data to each processing unit, and in one clock cycle of a first clock signal alternatively switches and outputs the first and second and supplies the alternatively switched first and second configuration data so that the alternatively switched first and second configuration data synchronizes with a periodic signal at each pipeline structure of the processor elements; and

a parallel/serial conversion unit for forwarding a number of inputs equal to the given number of tasks to the network in synchronization with the first clock signal;

wherein the switching unit generates configuration data into which configuration data of a different task is integrated; and

wherein the switching unit comprises;

a storage unit for storing the first and second configuration data of all tasks;

a sequence unit which designates the position of data in the storage unit; and

a task switching supply unit which switches the output of the sequence unit to the storage unit according to the task to be processed; and

wherein the parallel/serial conversion unit comprises;

a number of latches equal to the given number of tasks for holding the number of inputs in synchronization with the first clock signal;

a counter for counting clock cycles of a second clock signal with which each processing unit of each one of the processor elements operates, a frequency of the second clock signal being a frequency of the first clock signal multiplied by the given number; and

a selector for selecting and outputting one of the inputs held in the latches in accordance with an output of the counter.

11. A circuit for time division multiple processing, comprising:

a first reconfigurable circuit, comprising;

a plurality of first processor elements, each first processor element having a pipeline structure and at least one first processing unit in which configurations are changeable according to first configuration data to be supplied;

a first network in which the input and output of a plurality of said first processor elements are connected and which transfers data between the inputs and outputs according to second configuration data to be supplied;

a first switching unit that switches the first and second configuration data prepared for a number of given tasks in a predetermined order at a predetermined rate, outputs the switched first and second configuration data to each first processing unit, and in one clock cycle of a first clock signal alternatively switches and outputs the first and second configuration data and supplies the alternatively switched first and second configuration data so that the alternatively switched first and second configuration data synchronizes with a periodic signal at each pipeline structure of the first processor elements; and

a parallel/serial conversion unit for forwarding a number of inputs equal to the number of tasks to the first network in synchronization with the first clock signal;

a second reconfigurable circuit comprising;

a plurality of second processor elements, each second processor element having a pipeline structure and at least one second processing unit in which configurations are changeable according to third configuration data to be supplied;

a second network in which the inputs and outputs of a plurality of said second processor elements are connected and which transfers data between the inputs and outputs of the second processor elements according to fourth configuration data to be supplied; and

a second switching unit that switches the third and fourth configuration data prepared for the number of given tasks in a predetermined order at a predetermined rate, outputs the switched third and fourth configuration data to each second processing unit, and in one clock cycle alternatively switches and outputs the third and fourth configuration data and supplies the alternatively switched third and fourth configuration data so that the alternatively switched third and fourth configuration data synchronizes with the periodic signal at each pipeline structure of the second processor elements, in which a lag of a configuration switching cycle exists between the first reconfigurable circuit and the second reconfigurable circuit; and

a delay unit for adjusting the lag of the configuration switching cycle which is inserted between the network of the first reconfigurable circuit and the network of the second reconfigurable circuit;

wherein at least one of the first switching unit and the second switching unit comprises;

a storage unit for storing the first and second configuration data for every task;

an output position designation unit which forms a pair with the storage unit and designates the position of data to be outputted from the storage unit; and

a task switching unit for switching the output of the storage unit according to the task to be processed; and

wherein the parallel/serial conversion unit comprises;

a number of latches equal to the number of tasks for holding the number of inputs in synchronization with the first clock signal;

a counter for counting clock cycles of a second clock signal with which each processing unit of each one of the first processor elements operates, a frequency of the second clock signal being a frequency of the first clock signal multiplied by the number of tasks; and

a selector for selecting and outputting one of the inputs held in the latches in accordance with an output of the counter.

12. The reconfigurable circuit according to claim 11, comprising:

A serial/parallel conversion unit for outputting time division multiplex data supplied from the first network to a given number of output terminals.

13. The reconfigurable circuit according to claim 12, further comprising:

a timing adjustment unit for adjusting a timing of the outputted time division multiplex data in order to enable an output of the serial/parallel conversion unit to be connected to the given number of inputs of the parallel/serial conversion unit, and

wherein the serial/parallel conversion unit outputs processing data from the tasks in a predetermined order to the first processor elements.

14. The reconfigurable circuit according to claim 11, further comprising:

A correlation transfer unit for transferring data between different configuration phases.

15. The reconfigurable circuit according to claim 14, wherein

the correlation transfer unit comprises a selector in which the output of a processing unit of a transfer source is an input of the correlation transfer unit, and an output of the correlation transfer unit is connected to a desired transfer destination.

16. The reconfigurable circuit according to claim 11, further comprising:

a delay unit in the at least one first processing unit and in the at least one second processing unit in order to set configurations by replacing each configuration with a configuration of a next pipeline stage with one clock cycle delay.

17. A circuit for time division multiple processing, comprising:

a first reconfigurable circuit, comprising;

a plurality of first processor elements, each first processor element having a pipeline structure and at least one first processing unit in which configurations are changeable according to first configuration data to be supplied;

a first network in which the inputs and outputs of a plurality of said first processor elements are connected and which transfers data between the inputs and outputs according to second configuration data to be supplied;

a first switching unit that switches the first and second configuration data prepared for a number of given tasks in a predetermined order at a predetermined rate, outputs the switched first and second configuration data to each first processing unit, and in one clock cycle of a first clock signal alternatively switches and outputs the first and second configuration data and supplies the alternatively switched first and second configuration data so that the alternatively switched first and second configuration data synchronizes with a periodic signal at each pipeline structure of the first processor elements;

a first delay unit in the at least one first processing unit of each first processor element in order to set configurations by replacing each configuration with a configuration of the next pipeline stage with a one clock cycle delay; and

a parallel/serial conversion unit for forwarding a number of inputs equal to the number of tasks to the first network in synchronization with the first clock signal;

a second reconfigurable circuit, comprising;

a plurality of second processor elements, each second processor element having a pipeline structure and at least one second processing unit in which configurations are changeable according to third configuration data to be supplied;

a second network in which the inputs and outputs of a plurality of said second processor elements are connected and which transfers data between the inputs and outputs of the second processor elements according to fourth configuration data to be supplied;

a second switching unit which switches the third and fourth configuration data prepared for the number of given tasks in a predetermined order at a predetermined rate, outputs the switched third and fourth configuration data to each second processing unit, and in one clock cycle alternatively switches and outputs the third and fourth configuration data and supplies the alternatively switched third and fourth configuration data so that the alternatively switched third and fourth configuration data synchronizes with the periodic signal at each pipeline structure of the second processor elements; and

a second delay unit in the at least one second processing unit of each second processor element in order to set configurations by replacing each configuration with a configuration of the next pipeline stage with a one clock cycle delay, in which a lag of a configuration switching cycle exists between the first reconfigurable circuit and the second reconfigurable circuit;

wherein

the second delay unit adjusts the lag of the configuration switching cycle which is inserted between the network of the first reconfigurable circuit and the network of the second reconfigurable circuit; and

wherein the parallel/serial conversion unit comprises;

a number of latches equal to the number of tasks for holding the number of inputs in synchronization with the first clock signal;

a counter for counting clock cycles of a second clock signal with which each processing unit of each one of the first processor elements operates, a frequency of the second clock signal being a frequency of the first clock signal multiplied by the number of tasks; and

a selector for selecting and outputting one of the inputs held in the latches in accordance with an output of the counter.

18. A circuit for time division multiple processing, comprising:

a first reconfigurable circuit comprising;

a plurality of first processor elements, each first processor element having a pipeline structure and at least one first processing unit in which configurations are changeable according to first configuration data to be supplied;

a first network in which the inputs and outputs of a plurality of said first processor elements are connected and which transfers data between the inputs and outputs according to second configuration data to be supplied;

a first switching unit that switches the first and second configuration data prepared for a number of tasks in a predetermined order at a predetermined rate, outputs the switched first and second configuration data to each first processing unit, and in one clock cycle of a first clock signal alternatively switches and outputs the first and second configuration data and supplies the alternatively switched first and second configuration data so that the alternatively switched first and second configuration data synchronizes with a periodic cycle at each pipeline structure of the first processor elements; and

a parallel/serial conversion unit for forwarding a number of inputs equal to the number of tasks to the first network in synchronization with the first clock signal;

a second reconfigurable circuit comprising;

a plurality of second processor elements, each second processor element having a pipeline structure and at least one second processing unit in which configurations are changeable according to third configuration data to be supplied;

a second network in which the inputs and outputs of a plurality of said second processor elements are connected and which transfers data between the inputs and outputs of the second processor elements according to fourth configuration data to be supplied; and

a second switching unit that switches the third and fourth configuration data prepared for the number of tasks in a predetermined order at a predetermined rate, outputs the switched third and fourth configuration data to each second processing unit, and in one clock cycle alternatively switches and outputs the third and fourth configuration data and supplies the alternatively switched third and fourth configuration data so that the alternatively switched third and fourth configuration data synchronizes with a periodic cycle at each pipeline structure of the second processor elements, in which a lag of a configuration switching cycle exists between the first reconfigurable circuit and the second reconfigurable circuit; and

a delay unit for adjusting the lag of the configuration switching cycle which is inserted between the network of the first reconfigurable circuit and the network of the second reconfigurable circuit;

wherein at least one of the first switching unit and the second switching unit comprises;

a storage unit for storing the first and second configuration data of all tasks;

a sequence unit which designates the position of data in the storage unit; and

a task switching supply unit which switches the output of the sequence unit to the storage unit according to the task to be processed; and

wherein the parallel/serial conversion unit comprises;

a number of latches equal to the number of tasks for holding the number of inputs in synchronization with the first clock signal;

a counter for counting clock cycles of a second clock signal with which each processing unit of each one of the first processor elements operates, a frequency of the second clock signal being a frequency of the first clock signal multiplied by the number of task; and

a selector for selecting and outputting one of the inputs held in the latches in accordance with an output of the counter.