Optimizing preemptible read-copy update for low-power usage by avoiding unnecessary wakeups

• US 8,055,918 B2
• Filed: 04/03/2008
• Issued: 11/08/2011
• Est. Priority Date: 04/03/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Triplett, Joshua A., McKenney, Paul E.
• Primary Examiner(s): PATEL, NITIN C
• Application Number:
  US12/061,819
• Publication Number:
  US 20090254764A1
• Time in Patent Office: 1,314 Days
• Field of Search: 713/300, 713/323
• US Class Current: 713/300
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/522 Barrier synchronisation

Abstract

A technique for low-power detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element have been removed. A grace period processing action is implemented that requires a response from a processor that may be running a preemptible reader of said shared data element before further grace period processing can proceed. A power and reader status of the processor is also determined. Grace period processing may proceed despite the absence of a response from the processor if the power and reader status indicates that an actual response from the processor is unnecessary.

Claims

1. A method for low-power detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element are removed, comprising:

implementing a grace period processing action that requires a response from a processor that may be running a preemptible reader of said shared data element before further grace period processing can proceed;

determining a power and reader status of said processor; and

proceeding with grace period processing without said response if said power and reader status indicates that said response is unnecessary.

2. A method in accordance with claim 1, wherein said power and reader status comprises said processor being in either of 1) a non-low-power state or a low-power state with concurrent reader processing, or 2) a low-power state without concurrent reader processing.

3. A method in accordance with claim 2, wherein said low-power state includes said processor being in a dynamic tick timer mode and wherein said low-power state with concurrent reader processing includes to said processor handling an interrupt in dynamic tick timer mode using a reader.

4. A method in accordance with claim 1, wherein said power and reader status is determined by determining an initial power and reader status when said grace period processing action is taken and comparing said initial power and reader status to a current power and reader status.

5. A method in accordance with claim 4, wherein said processor is designated as having provided said response upon said power and reader status indicating that 1) said processor has remained in a low-power state without reader execution since said grace period processing action, or 2) said processor has passed through or entered a low-power state without reader execution since said grace period processing action, or 3) said processor has entered an execution state that is tantamount to said response being provided.

6. A method in accordance with claim 1, wherein said power and reader status is determined from a power and reader status indicator maintained by said processor that is manipulated when said processor enters or leaves a low-power state, or enters or leaves a reader processing state while in a low-power state.

7. A system adapted for low-power detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element are removed, comprising:

one or more processors;

a memory coupled to said one or more processors, said memory including a computer useable medium tangibly embodying at least one program of instructions executable by said processor to perform operations, comprising;

implementing a grace period processing action that requires a response from a processor that may be running a preemptible reader of said shared data element before further grace period processing can proceed;

determining a power and reader status of said processor; and

proceeding with grace period processing without said response if said power and reader status indicates that said response is unnecessary.

8. A system in accordance with claim 7, wherein said power and reader status comprises said processor being in either of 1) a non-low-power state or a low-power state with concurrent reader processing, or 2) a low-power state without concurrent reader processing.

9. A system in accordance with claim 8, wherein said low-power state includes said processor being in a dynamic tick timer mode and wherein said low-power state with concurrent reader processing includes to said processor handling an interrupt in dynamic tick timer mode using a reader.

10. A system in accordance with claim 7, wherein said power and reader status is determined by determining an initial power and reader status when said grace period processing action is taken and comparing said initial power and reader status to a current power and reader status.

11. A system in accordance with claim 10, wherein said processor is designated as having provided said response upon said power and reader status indicating that 1) said processor has remained in a low-power state without reader execution since said grace period processing action, or 2) said processor has passed through or entered a low-power state without reader execution since said grace period processing action, or 3) said processor has entered an execution state that is tantamount to said response being provided.

12. A system in accordance with claim 7, wherein said power and reader status is determined from a power and reader status indicator maintained by said processor that is manipulated when said processor enters or leaves a low-power state, or enters or leaves a reader processing state while in a low-power state.

13. A computer program product for low-power detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element are removed, comprising:

one or more machine-useable non-transitory media;

logic provided by said one or more media for programming a data processing platform to operate as by;

implementing a grace period processing action that requires a response from a processor that may be running a preemptible reader of said shared data element before further grace period processing can proceed;

determining a power and reader status of said processor; and

proceeding with grace period processing without said response if said power and reader status indicates that said response is unnecessary.

14. A computer program product in accordance with claim 13, wherein said power and reader status comprises said processor being in either of 1) a non-low-power state or a low-power state with concurrent reader processing, or 2) a low-power state without concurrent reader processing.

15. A computer program product in accordance with claim 14, wherein said low-power state includes said processor being in a dynamic tick timer mode and wherein said low-power state with concurrent reader processing includes to said processor handling an interrupt in dynamic tick timer mode using a reader.

16. A computer program product in accordance with claim 13, wherein said power and reader status is determined by determining an initial power and reader status when said grace period processing action is taken and comparing said initial power and reader status to a current power and reader status.

17. A computer program product in accordance with claim 16, wherein said processor is designated as having provided said response upon said power and reader status indicating that 1) said processor has remained in a low-power state without reader execution since said grace period processing action, or 2) said processor has passed through or entered a low-power state without reader execution since said grace period processing action, or 3) said processor has entered an execution state that is tantamount to said response being provided.

18. A computer program product in accordance with claim 13, wherein said power and reader status is determined from a power and reader status indicator maintained by said processor that is manipulated when said processor enters or leaves a low-power state, or enters or leaves a reader processing state while in a low-power state.

19. A computer program product for low-power detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element are removed, comprising:

one or more machine-useable non-transitory media;

logic provided by said one or more media for programming a data processing platform to operate as by;

implementing a grace period processing action that requires a response from a processor that may be running a preemptible reader of said shared data element before further grace period processing can proceed;

determining a power and reader status of said processor;

proceeding with grace period processing without said response if said power and reader status indicates that said response is unnecessary;

said power and reader status comprising said processor being in either of

     1) a non-low-power state or a low-power state with concurrent reader processing, or

     2) a low-power state without concurrent reader processing;

said low-power state including said processor being in a dynamic tick timer mode and said low-power state with concurrent reader processing including said processor handling an interrupt in dynamic tick timer mode using a reader; and

said power and reader status being determined from a power and reader status indicator maintained by said processor that is manipulated when said processor enters or leaves a low-power state, or enters or leaves a reader processing state while in a low-power state.

20. A computer program product in accordance with claim 19, wherein said power and reader status is determined by determining an initial power and reader status when said grace period processing action is taken and comparing said initial power and reader status to a current power and reader status, and wherein said processor is designated as having provided said response upon said power and reader status indicating that 1) said processor has remained in a low-power state without reader execution since said grace period processing action, or 2) said processor has passed through or entered a low-power state without reader execution since said grace period processing action, or 3) said processor has entered an execution state that is tantamount to said response being provided.