Semiconductor integrated circuit device having fail-safe mode and memory control method
First Claim
1. A semiconductor integrated circuit device, comprising:
- a flash memory;
a processor which instructs a write operation, an erase operation, and an erase verify operation following the erase operation to the flash memory; and
a flash control unit which executes, in a normal mode, a writing to the flash memory based on a write command from the processor, and executes, in a fail-safe mode, the writing to the flash memory and correcting of an error of a written data based on the write command from the processor,wherein the normal mode is shifted to the fail-safe mode when the erase verify operation in the normal mode indicates a defect,wherein the flash control unit includes;
an error correction code (ECC) encoder which generates an error correction code for data written in the flash memory, write data being written into the flash memory along with the error correction code; and
an ECC decoder which corrects an error based on a read data read from the flash memory,wherein, in the normal mode, when retries of a rewrite operation exceed a specified count, the flash memory is prohibited from being used, as a write detect, andwherein, in the fail-safe mode, when retries of the rewrite operation exceed the specified count, the ECC decoder is activated to perform the erase verify operation.
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Accused Products
Abstract
An integrated circuit device contains a flash memory, a flash control unit for controlling the rewriting and reading on the flash memory, and a processor unit. The processor unit includes a normal mode and a fail-safe mode as the operating states. In normal mode, when a defect is detected during the verify operation after writing data onto the flash memory then any further use of the flash memory is stopped. In fail-safe-mode, when a defect is detected during the verify operation after writing data onto the flash memory, the error is corrected and flash memory usage continues. The operating state is normal mode, and when the verify operation detects a defect after normal mode erase operation, the operation shifts to fail-safe mode.
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Citations
14 Claims
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1. A semiconductor integrated circuit device, comprising:
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a flash memory; a processor which instructs a write operation, an erase operation, and an erase verify operation following the erase operation to the flash memory; and a flash control unit which executes, in a normal mode, a writing to the flash memory based on a write command from the processor, and executes, in a fail-safe mode, the writing to the flash memory and correcting of an error of a written data based on the write command from the processor, wherein the normal mode is shifted to the fail-safe mode when the erase verify operation in the normal mode indicates a defect, wherein the flash control unit includes; an error correction code (ECC) encoder which generates an error correction code for data written in the flash memory, write data being written into the flash memory along with the error correction code; and an ECC decoder which corrects an error based on a read data read from the flash memory, wherein, in the normal mode, when retries of a rewrite operation exceed a specified count, the flash memory is prohibited from being used, as a write detect, and wherein, in the fail-safe mode, when retries of the rewrite operation exceed the specified count, the ECC decoder is activated to perform the erase verify operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory control method for a semiconductor integrated circuit device including a flash memory, a memory control unit, and a processor, said method comprising:
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operating the flash memory in a normal mode; operating the flash memory in a fail-safe mode; and shifting the normal mode to the fail-safe mode, and wherein the operating the flash memory in the normal mode includes; performing a write operation to the flash memory; performing an erase operation; and performing an erase verify operation; wherein the operating the flash memory in the fail-safe mode includes; performing the write operation to the flash memory; and correcting an error of a written data, wherein the shifting the normal mode to the fail-safe mode is executed when the erase verify operation in the normal mode indicates a defect, wherein the erase verify operation includes; verifying the data written without performing an error correction based on an error correction code; performing an error correction of data written based on the error correction code, as an error correction code (ECC) verify; and confirming an erasure state of an area erased by the erase operation, wherein the normal mode includes; retrying to write the data, until a number of the erase verify operation reaches a specified number of times; and stopping using the flash memory as a write defect, when the retrying exceeds the specified number of times, and wherein the fail-safe mode includes; retrying to write the data, until a number of the erase verify operation reaches a specified number of times; and retrying to write data written by using the ECC verify, when the retrying exceeds the specified number of times. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification