Semiconductor integrated circuit device having fail-safe mode and memory control method

• US 8,055,957 B2
• Filed: 05/09/2008
• Issued: 11/08/2011
• Est. Priority Date: 05/22/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kondo, Takao
• Primary Examiner(s): Tabone, Jr.; John J
• Application Number:
  US12/149,915
• Publication Number:
  US 20080294938A1
• Time in Patent Office: 1,278 Days
• Field of Search: 714/48, 714/718, 714/719, 714/710, 714/754, 714/764, 365/185.09, 365/185.29, 365/185.33, 365/200, 365/201
• US Class Current: 714/710
• CPC Class Codes: G06F 11/0796 Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G11C 2029/0409 Online test

Abstract

An integrated circuit device contains a flash memory, a flash control unit for controlling the rewriting and reading on the flash memory, and a processor unit. The processor unit includes a normal mode and a fail-safe mode as the operating states. In normal mode, when a defect is detected during the verify operation after writing data onto the flash memory then any further use of the flash memory is stopped. In fail-safe-mode, when a defect is detected during the verify operation after writing data onto the flash memory, the error is corrected and flash memory usage continues. The operating state is normal mode, and when the verify operation detects a defect after normal mode erase operation, the operation shifts to fail-safe mode.

Claims

1. A semiconductor integrated circuit device, comprising:

a flash memory;

a processor which instructs a write operation, an erase operation, and an erase verify operation following the erase operation to the flash memory; and

a flash control unit which executes, in a normal mode, a writing to the flash memory based on a write command from the processor, and executes, in a fail-safe mode, the writing to the flash memory and correcting of an error of a written data based on the write command from the processor,

wherein the normal mode is shifted to the fail-safe mode when the erase verify operation in the normal mode indicates a defect,

wherein the flash control unit includes;

an error correction code (ECC) encoder which generates an error correction code for data written in the flash memory, write data being written into the flash memory along with the error correction code; and

an ECC decoder which corrects an error based on a read data read from the flash memory,

wherein, in the normal mode, when retries of a rewrite operation exceed a specified count, the flash memory is prohibited from being used, as a write detect, and

wherein, in the fail-safe mode, when retries of the rewrite operation exceed the specified count, the ECC decoder is activated to perform the erase verify operation.

2. The semiconductor integrated circuit device according to claim 1, wherein the flash memory includes a substitute block, and

wherein, when a defect is detected in the erase verify operation after the erase operation, the flash control unit changes an access address in the flash memory to access the substitute block instead of a flash memory block that includes the defect.

3. The semiconductor integrated circuit device according to claim 2, wherein the flash memory includes:

an extra area which stores a redundancy information indicating a block in the flash memory where the defect is detected; and

an address register for changing the access address based on the redundancy information.

4. The semiconductor integrated circuit device according to claim 3, wherein the flash control unit includes:

a redundancy register which stores the redundancy information; and

a reset sequence control unit which reads out the redundancy information in the extra area and stores the redundancy information in the redundancy register, before an initialization of the processor.

5. The semiconductor integrated circuit device according to claim 1, wherein the flash memory includes multiple sections, and

wherein, when an area capable to write data in a first section among said multiple sections falls below a specified threshold, a valid data in the first section is copied into a second section, and then the valid data in the first section is erased.

6. The semiconductor integrated circuit device according to claim 5, wherein each of the multiple sections includes a header information, the header information including a plurality of flags.

7. The semiconductor integrated circuit device according to claim 1, wherein the processor instructs a write verify operation following the write operation, and

wherein the normal mode is not shifted to the fail-safe mode when the write verify operation in the normal mode indicates a defect.

8. A memory control method for a semiconductor integrated circuit device including a flash memory, a memory control unit, and a processor, said method comprising:

operating the flash memory in a normal mode;

operating the flash memory in a fail-safe mode; and

shifting the normal mode to the fail-safe mode, and

wherein the operating the flash memory in the normal mode includes;

performing a write operation to the flash memory;

performing an erase operation; and

performing an erase verify operation;

wherein the operating the flash memory in the fail-safe mode includes;

performing the write operation to the flash memory; and

correcting an error of a written data,

wherein the shifting the normal mode to the fail-safe mode is executed when the erase verify operation in the normal mode indicates a defect,

wherein the erase verify operation includes;

verifying the data written without performing an error correction based on an error correction code;

performing an error correction of data written based on the error correction code, as an error correction code (ECC) verify; and

confirming an erasure state of an area erased by the erase operation,

wherein the normal mode includes;

retrying to write the data, until a number of the erase verify operation reaches a specified number of times; and

stopping using the flash memory as a write defect, when the retrying exceeds the specified number of times, and

wherein the fail-safe mode includes;

retrying to write the data, until a number of the erase verify operation reaches a specified number of times; and

retrying to write data written by using the ECC verify, when the retrying exceeds the specified number of times.

9. The memory control method according to claim 8, wherein the flash memory includes a substitute block, and

wherein the memory control method further comprises:

converting an access address to access the substitute block instead of a defective block on the flash memory when the erase verify operation detects a defect after performing the erase operation.

10. The memory control method according to claim 9, wherein the flash memory comprises an extra area, and

wherein the memory control method further comprises:

storing a redundancy information indicating a block of the flash memory where a defect was detected, onto the extra area; and

converting the access address based on the redundancy information read out from the extra area.

11. The memory control method according to claim 10, further comprising:

reading the redundancy information stored in the extra area; and

storing that redundancy information in a register before an initialization of a processor.

12. The memory control method according to claim 8, further comprising:

copying a valid data within a first section onto a second section, when an area for writing data within a first section in the flash memory falls below a specified threshold value; and

erasing the data in the first section to set a blank state.

13. The memory control method according to claim 12, wherein each of the first and second sections comprises a header information, said header information including a plurality of flags, each of the flags being stored at a respective address corresponding to different word lines.

14. The memory control method according to claim 8, wherein the operating the flash memory in the normal mode further includes:

performing a write verify operation following the performing the write operation, and

wherein the shifting the normal mode to the fail-safe mode is not executed when the write verify operation in the normal mode indicates a defect.