Channel constrained code aware interleaver
First Claim
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1. An interleaver comprising:
- a first input path;
a second input path;
a multiplexer having a first input coupled to the first input path, a second input coupled to the second input path, a control input for receiving a control signal, and an output;
a memory having a write input coupled to the output of the multiplexer and a read output; and
a FIFO having a write input coupled to the output of the memory and a read output, whereinthe memory comprises a plurality of interleaved sub-word (ISW) chunks, whereinthe ISW chucks are mapped from de-interleaved sub-word (DSW) chunks, whereinthe DSW chunks each comprises bits that have information and parity bits chosen from a plurality of code memory chunks in such a way that a chunk of consecutive κ
bits is randomly chosen from each code memory chunk.
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Abstract
An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.
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21 Claims
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1. An interleaver comprising:
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a first input path; a second input path; a multiplexer having a first input coupled to the first input path, a second input coupled to the second input path, a control input for receiving a control signal, and an output; a memory having a write input coupled to the output of the multiplexer and a read output; and a FIFO having a write input coupled to the output of the memory and a read output, wherein the memory comprises a plurality of interleaved sub-word (ISW) chunks, wherein the ISW chucks are mapped from de-interleaved sub-word (DSW) chunks, wherein the DSW chunks each comprises bits that have information and parity bits chosen from a plurality of code memory chunks in such a way that a chunk of consecutive κ
bits is randomly chosen from each code memory chunk. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An interleaver comprising:
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an input section that can be configured for a first operating mode or a second operating mode; a memory having an input coupled to the input section and an output; and a FIFO having an input coupled to the memory and an output for providing the addresses and the end of interleaver sub word signal to the appropriate read/write side where the interleaving operations are needed, wherein the memory comprises a plurality of interleaved sub-word (ISW) chunks, wherein the ISW chucks are mapped from de-interleaved sub-word (DSW) chunks, wherein the DSW chunks each comprises bits that have information and parity bits chosen from a plurality of code memory chunks in such a way that a chunk of consecutive κ
bits is randomly chosen from each code memory chunk. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A method of code aware interleaving, comprising:
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identifying parity locations and mapping parity bits in a de-interleaved sub-word (DSW) memory to an interleaved sub-word (ISW) memory; identifying information indices within the ISW memory that are by-lane constrained; identifying a set of indices in a ISW domain that satisfy code constraints according to equation
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Specification