Decoding device, encoding/decoding device and recording/reproducing device

• US 8,055,977 B2
• Filed: 10/24/2007
• Issued: 11/08/2011
• Est. Priority Date: 10/30/2006
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ito, Toshio
• Primary Examiner(s): KERVEROS, DEMETRIOS C
• Application Number:
  US11/977,266
• Publication Number:
  US 20080104481A1
• Time in Patent Office: 1,476 Days
• Field of Search: 714/758
• US Class Current: 714/758
• CPC Class Codes: G11B 20/1803 by redundancy in data representation
• CPC Class Codes: G11B 20/1866 by interleaving G11B20/1809 takes precedence
• CPC Class Codes: H03M 13/098 using single parity bit
• CPC Class Codes: H03M 13/11 using multiple parity bits
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2909 Product codes
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/453 wherein the candidate code words are obtained by an algebraic decoder, e.g. Chase decoding
• CPC Class Codes: H03M 13/455 using a set of erasure patterns or successive erasure decoding, e.g. generalized minimum distance [GMD] decoding
• CPC Class Codes: H03M 13/6343 Error control coding in combination with techniques for partial response channels, e.g. recording

Abstract

An encoding/decoding device corrects errors by concatenated codes of an ECC code and a parity code to prevent an increase in the circuit scale and to improve error correction performance. The device has encoders for creating a concatenation type encoded data by interleaving a data string into a plurality of blocks at every m (m≧2) bit, adding a parity of an error correcting code and adding a parity bit at every predetermined number of bits for preventing an increase in the circuit scale even if the data string is interleaved into a plurality of blocks, and a parity of error correcting code is generated. Also ECC decoding circuits for correcting an ECC decoded data string using the likeliness of a soft output decoder and parity check result are provided, so a deterioration of correction performance can also be prevented.

Claims

1. A decoder for decoding an encoded data string comprising error correction code words and a parity bit that is created for a predetermined number of bits of error correcting code words, the error correction code words comprising data string and a parity of the error correcting code that is generated from data string of each block of which the data string is interleaved into n (n≧

2) blocks at every m (m≧

2) bits, the decoder comprising;

a soft output decoder for decoding the encoded data string that is received to a code bit string and outputting the code bit string and the likelihood of each bit; and

an ECC decoding circuit for repeating an error correction decoding using an error correcting code of the code bit string from the soft output decoder, and a correction decoding of the code bit string based on the likelihood according to the error detection using the parity bit,

wherein the ECC decoding circuit comprises;

an ECC decoder for performing error correction using the error correcting code of the code bit string of the soft output decoder; and

a parity/likelihood correction unit for performing an error detection using the parity bit according to a failure of the decoding of the ECC decoder, and correcting the code bit string that is input to the ECC decoder depending on the likelihood according to the error detection result.

2. The decoder according to claim 1, further comprising:

a separation section for separating the parity bit from the code bit string of the soft output decoder and outputting the code bit string to the parity/likelihood correction unit;

an interleave section for interleaving the code bit string after the parity bit is separated into n (n≧

2) blocks of a data string at every m (m≧

2) bit; and

a data storage section for storing the interleaved data string of each block,

wherein the ECC decoder performs error correction of the data string of each block of the data storage section using the error correcting code, and the parity/likelihood correction unit corrects the data string of the data storage unit.

3. The decoder according to claim 2, wherein when the decoding fails, the parity/likelihood correction unit receives an identifier of the block in which the decoding fails from the ECC decoder, and performs correction using the likelihood targeting the m bits of data of which error is detected by the parity bit of the block in which the decoding fails.

4. The decoder according to claim 3, wherein the parity/likelihood correction unit calculates a parity bit for every m×

n bit of the error correcting code word of the ECC decoder, and specifies the m bits of data of which error is detected by comparison of the calculated parity bit for every m×

n bit and the corresponding separated parity bit.

5. The decoder according to claim 4, wherein the parity/likelihood correction unit calculates a parity error value from an addition result of the calculated parity bit after the error detection and the separated parity bit, and specifies an error generation position at m bits of the data by comparison of the parity bits.

6. The decoder according to claim 4, wherein the parity/likelihood correction unit specifies an error candidate bit based on the likelihood of each bit of the error-detected m bits.

7. The decoder according to claim 5, wherein the parity/likelihood correction unit further comprises a table of error candidate positions corresponding to the parity error values according to a generation polynomial of the parity bit,

and wherein the parity/likelihood correction unit refers to the table by the parity error value, and specifies the error generation position of the m bits of data based on the reference result and the likelihood.

8. The decoder according to claim 3, wherein the parity/likelihood correction unit extracts a bit position of which likelihood is relatively low based on the likelihood of each bit out of the m bits as the correction candidate in m bit units.

9. The decoder according to claim 2, wherein the parity/likelihood correction unit flips the data at the error generation position of the m bits of data, and updates the data string of the data storage unit.

10. The decoder according to claim 1, wherein the error correction code of the encoding data string is a Reed Solomon code.

11. An encoding/decoding device comprising:

an encoder comprising;

an ECC encoder for creating an error correcting code word by interleaving a data string into n (n≧

2) blocks of a data string at every m (m≧

2) bit, generating a parity of an error correcting code from the interleaved data string of each block, and adding the parity of the error correcting code of each block to the data string; and

a parity encoder for creating a parity bit at every predetermined number of bits of error correcting code words, and adding the parity bit to error correcting code words;

a decoder comprising;

a soft output decoder for decoding the encoded data string that is received to a code bit string, and outputting the code bit string and the likelihood of each bit; and

an ECC decoding circuit for repeating an error correction decoding using an error correcting code of the code bit string of the soft output decoder and a correction decoding of the code bit string based on the likelihood according to the error detection using the parity bit,

wherein the ECC decoding circuit comprises;

an ECC decoder for performing error correction using the error correcting code of the code bit string of the soft output decoder; and

a parity/likelihood correction unit for performing an error detection using the parity bit according to the failure of the decoding of the ECC decoder, and correcting the code bit string that is input to the ECC decoder depending on the likelihood according to the error detection result.

12. The encoding/decoding device according to claim 11, wherein the error correcting code is a Reed Solomon code.

13. A recording/reproducing device comprises:

a head for writing and reading data to/from a storage medium;

an ECC encoder for interleaving a data string into n (n≧

2) blocks of a data string, which is to be written to the storage medium, at every m (m≧

2) bit, generating a parity of an error correcting code from the interleaved data string of each block, and adding the parity of the error correcting code of each block to the data string;

a parity encoder for creating a parity bit at every predetermined number of bits of error correcting code words, adding the parity bit to error correcting code words and outputting the result to the head;

a soft output decoder for decoding an encoded data string read from the head to a code bit string, and outputting the code bit string and the likelihood of each bit; and

an ECC decoding circuit for repeating an error correction decoding using the parity of the error correcting code of the code bit string of the soft output decoder, and a correction decoding of the code bit string based on the likelihood according to the error detection using the parity bit,

wherein the ECC decoding circuit comprises;

an ECC decoder for performing error correction using the error correcting code of the code bit string of the soft output decoder; and

a parity/likelihood correction unit for performing an error detection using the parity bit according to a failure of the decoding of the ECC decoder, and correcting the code bit string that is input to the ECC decoder depending on the likelihood according to the error detection result.

14. The recording/reproducing device according to claim 13, wherein the error correcting code is a Reed Solomon code.