Integration scheme for strained source/drain CMOS using oxide hard mask

• US 8,058,120 B2
• Filed: 07/28/2010
• Issued: 11/15/2011
• Est. Priority Date: 09/18/2009
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Ning, Xian Jie, Zhu, Bei
• Primary Examiner(s): Geyer; Scott B
• Application Number:
  US12/845,676
• Publication Number:
  US 20110070701A1
• Time in Patent Office: 475 Days
• Field of Search: None
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method for forming a semiconductor integrated circuit device, e.g., CMOS, includes providing a semiconductor substrate having a first well region and a second well region. The method further includes forming a dielectric layer overlying the semiconductor substrate, the first well region and the second well region, and forming a polysilicon gate layer (e.g., doped polysilicon) overlying the dielectric layer. The polysilicon gate layer is overlying a first channel region in the first well region and a second channel region in the second well region. The method includes forming a hard mask (e.g., silicon dioxide) overlying the polysilicon gate layer and patterning the polysilicon gate layer and the hard mask layer to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region. Next, the method separately forms strained regions in the first and second well regions.

Claims

1. A method for forming a semiconductor integrated circuit device comprising:

providing a semiconductor substrate including a first well region and a second well region;

forming a dielectric layer overlying the semiconductor substrate including the first well region and the second well region;

forming a polysilicon gate layer overlying the dielectric layer, the polysilicon gate layer being overlying a first channel region in the first well region and a second channel region in the second well region in the semiconductor substrate;

forming a hard mask overlying the polysilicon gate layer;

patterning the polysilicon gate layer, including the hard mask layer, to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region;

forming a liner layer overlying the first gate structure and the second gate structure and overlying a first source region and a first drain region in the first well region and a second source region and a second drain region in the second well region;

forming a spacer dielectric layer overlying the liner layer, the spacer dielectric layer including a first portion overlying the first gate structure and a second portion overlying the second gate structure;

protecting the second gate structure, including the second source and drain regions, and the second portion of the spacer dielectric layer provided in the second well region using a second photoresist mask material;

patterning the first portion of the spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges while the second photoresist mask material protects the second portion of the spacer dielectric layer and the second gate structure, including the second source and drain regions in the second well region;

etching a first source region and a first drain region adjacent to the first gate structure using the hard mask layer and the first sidewall spacers as a protective layer;

depositing a silicon germanium fill material into the first source region and the first drain region to fill the etched first source region and the etched first drain region while causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region;

removing the second photoresist masking material;

protecting the first gate structure, including first source/drain regions, and the first portion of the spacer dielectric layer provided in the first well region using a first photoresist mask material;

patterning the second portion of the spacer dielectric layer to form second sidewall spacer structures on the second gate structure, including the second edges while the first photoresist mask material protects the first gate structure, including the first source/drain regions in the first well region;

etching a second source region and a second drain region adjacent to the second gate structure using the hard mask layer and the second sidewall spacers as a protective layer;

depositing a silicon carbide fill material into the second source region and the second drain region to fill the etched second source region and the etched second drain region while causing the second channel region between the second source region and the second drain region to be strained in tensile mode from at least the silicon carbide material formed in the second source region and the second drain region; and

removing the first photoresist masking material.

2. The method of claim 1 wherein the dielectric layer is less than 300 Angstroms.

3. The method of claim 1 wherein the semiconductor substrate comprises essential silicon material.

4. The method of claim 1 wherein the silicon germanium material is single crystalline.

5. The method of claim 1 wherein the silicon germanium has a ratio of silicon/germanium of 10% to 20%.

6. The method of claim 1 wherein the selectively removing comprises a wet etch including a hydrogen fluoride species.

7. The method of claim 1 wherein the hard mask is a thickness of about 200 to about 400 Angstroms.

8. The method of claim 1 wherein the depositing is provided using an epitaxial reactor.

9. The method of claim 1 wherein the compressive mode increases a mobility of holes in the first channel region.

10. The method of claim 1 wherein the hard mask comprises a silicon dioxide, a silicon rich oxide, or oxide rich silicon oxynitride.

11. The method of claim 1 wherein the spacer dielectric layer comprises an oxide bearing material.

12. The method of claim 1 wherein the spacer dielectric layer comprises an oxide on nitride on oxide material.

13. The method of claim 1 wherein the spacer dielectric layer comprises an oxide on nitride material.

14. The method of claim 1 wherein the blanket layer of silicon oxide has a thickness of about 100 Angstroms to about 500 Angstroms.

15. The method of claim 1 wherein the liner layer comprises a TEOS material having a thickness of greater than 100 Angstroms.