Method of forming a nitrogen-enriched region within silicon-oxide-containing masses

• US 8,058,130 B2
• Filed: 08/22/2008
• Issued: 11/15/2011
• Est. Priority Date: 08/07/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S., Rueger, Neal R., Moore, John T.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US12/196,988
• Publication Number:
  US 20090215253A1
• Time in Patent Office: 1,180 Days
• Field of Search: 438/287, 438/197, 438/585
• US Class Current: 438/287
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.

Claims

1. A method of forming a nitrogen-enriched region within a silicon-oxide-containing mass, comprising:

providing the silicon-oxide-containing mass over a substrate;

the silicon-oxide-containing mass having a bare upper surface extending to a lower surface in physical contact with the substrate;

forming a nitrogen-enriched region within an upper third of the mass; and

after forming the nitrogen-enriched region, thermally annealing the nitrogen within the nitrogen-enriched region, while the bare upper surface of the silicon-oxide-containing mass remains bare, to bond at least some of the nitrogen to silicon proximate the nitrogen;

the nitrogen-enriched region remaining confined to the upper third of the silicon-oxide-containing mass during the annealing.

2. The method of claim 1 wherein the nitrogen-enriched region is formed only in the upper fourth of the mass and remains confined to the upper fourth of the mass during the annealing.

3. The method of claim 1 wherein the nitrogen-enriched region is formed only in the upper fifth of the mass by the exposing and remains confined to the upper fifth of the mass during the annealing.

4. The method of claim 1 wherein the mass has a thickness of no greater than about 60 Å

.

5. The method of claim 1 wherein the mass has a thickness of from between about 5Å

and 60 Å

.

6. The method of claim 1 wherein the annealing comprises thermal processing at a temperature of about 700°

C. for a time of about 30 seconds.

7. The method of claim 1 wherein the annealing comprises thermal processing at a temperature of about 1050°

C. for a time of about 5 seconds.

8. The method of claim 1 wherein the annealing comprises rapid thermal processing at a ramp rate of at least about 50°

C./sec to a process temperature of less than 1000°

C., with the process temperature being maintained for at least about 30 seconds.

9. The method of claim 1 further comprising forming a conductive mass upon the upper surface of the silicon-oxide-containing mass.

10. The method of claim 1 wherein the silicon-oxide-containing mass comprises silicon dioxide.

11. The method of claim 1 wherein the silicon-oxide-containing mass comprises borophosphosilicate glass.