Substrate bonding with metal germanium silicon material

• US 8,058,143 B2
• Filed: 01/21/2009
• Issued: 11/15/2011
• Est. Priority Date: 01/21/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Montez, Ruben B., Pamatat, Alex P.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): JEFFERSON, QUOVAUNDA
• Application Number:
  US12/356,939
• Publication Number:
  US 20100181676A1
• Time in Patent Office: 1,028 Days
• Field of Search: 438/455, 438/456, 438117-119, 438/458, 438/FOR.412, 438/FOR.438, 438/FOR.489, 257/E21.088, 257/E21.122, 257/E21.496, 257/E21.22, 257/E21.129, 257/E21.48
• US Class Current: 438/456
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/022 Protective coating, i.e. protective bond-through coating
• CPC Class Codes: H01L 2224/036 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/0391 Forming a passivation layer after forming the bonding area
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05638 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/2745 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/27452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/2746 Plating
• CPC Class Codes: H01L 2224/276 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/29013 being rectangular or square
• CPC Class Codes: H01L 2224/29016 in side view
• CPC Class Codes: H01L 2224/29083 Three-layer arrangements
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29117 : the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
• CPC Class Codes: H01L 2224/29124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29138 : the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/29144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/29157 : Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/29166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/29169 : Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/29181 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/29184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32502 : comprising an eutectic alloy
• CPC Class Codes: H01L 2224/32506 : comprising an eutectic alloy
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83411 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/83424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/83444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/83455 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/83457 : Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/83466 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/83469 : Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/83481 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/83484 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/10157 : at the active surface
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/164 : Material

Abstract

A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electromechanical system (MEMS) device. On the second substrate is formed a first layer comprising silicon. A second layer comprising germanium and silicon is formed on the first layer. A third layer comprising germanium is formed on the second layer. The third layer is brought into contact with the layer including metal. Heat (and pressure in some embodiments) is applied to the third layer and the layer including metal to form a mechanical bond material between the first substrate and the second substrate in which the mechanical bond material is electrically conductive. In the case of the mechanical bond surrounding a semiconductor device such as a MEMS, the mechanical bond can be particularly advantageous as a hermetic seal for protecting the MEMS.

Claims

1. A method, comprising:

forming a layer including metal over a first substrate;

providing a second substrate;

forming a first layer comprising silicon supported by the second substrate,

forming a second layer comprising germanium and silicon on the first layer;

forming a third layer comprising germanium on the second layer;

contacting the third layer to the layer including metal; and

after contacting the third layer to the layer including metal, forming a mechanical bonding material between the first substrate and the second substrate, wherein the forming a mechanical bonding material includes applying heat to the third layer and the layer including metal, wherein the bonding material includes a metal of the layer including metal and material of the third layer;

forming a semiconductor device over one of the first substrate or the second substrate prior to the contacting, wherein the bonding material surrounds the semiconductor device.

2. The method of claim 1, wherein the metal of the layer including metal is aluminum.

3. The method of claim 2, wherein the mechanical bonding material includes a material that is a ternary system including aluminum, silicon, and germanium.

4. The method of claim 1 wherein the forming the mechanical bonding material includes applying a bonding force pressure to the first substrate and the second substrate.

5. The method of claim 4 wherein the bonding force pressure is greater than 5000 milibars.

6. The method of claim 1 wherein the applying heat includes applying heat at a temperature of 500 C. or less.

7. The method of claim 1, wherein:

the step of forming the first layer is further characterized as forming the first layer to a thickness less than that of the third layer;

the step of forming the second layer is further characterized as forming the second layer to a thickness less than that of the third layer.

8. The method of claim 1, wherein a percentage of aluminum of the layer including metal is 98% or greater by atomic weight.

9. The method of claim 1, wherein the third layer comprises polycrystalline germanium.

10. The method of claim 1, wherein the bonding material hermetically seals the semiconductor device between the first substrate and the second substrate.

11. The method of claim 1, the method further comprising after forming the mechanical bonding material, singulating the first substrate and the second substrate into a plurality of die with each die including a semiconductor device hermetically sealed between a portion of the first substrate and a portion of the second substrate with a mechanical bonding material formed during the forming the mechanical bonding material.

12. The method of claim 1, A method, comprising:

forming a layer including metal over a first substrate;

providing a second substrate;

forming a first layer comprising silicon supported by the second substrate,

forming a second layer comprising germanium and silicon on the first layer;

forming a third layer comprising germanium on the second layer;

contacting the third layer to the layer including metal;

after contacting the third layer to the layer including metal, forming a mechanical bonding material between the first substrate and the second substrate, wherein the forming a mechanical bonding material includes applying heat to the third layer and the layer including metal, wherein the bonding material includes a metal of the layer including metal and material of the third layer;

wherein the steps of forming the first layer, the second layer, and the third layer are further characterized by the first layer, the second layer, and the third layer being polycrystalline.

13. A method, comprising:

forming a layer including metal over a first substrate;

providing a second substrate;

forming a first layer comprising silicon supported by the second substrate,

forming a second layer comprising germanium and silicon on the first layer;

forming a third layer comprising germanium on the second layer;

contacting the third layer to the layer including metal;

after contacting the third layer to the layer including metal, forming a mechanical bonding material between the first substrate and the second substrate, wherein the forming a mechanical bonding material includes applying heat to the third layer and the layer including metal, wherein the bonding material includes a metal of the layer including metal and material of the third layer; and

forming a layer of polysilicon over the first substrate prior to forming the layer including metal, wherein the step of forming the layer including metal is further characterized as the layer including metal being formed on the layer of polysilicon.

14. A method, comprising:

forming a layer including metal over a first substrate;

providing a second substrate;

forming a first layer comprising silicon supported by the second substrate,

forming a second layer comprising germanium and silicon on the first layer;

forming a third layer comprising germanium on the second layer;

contacting the third layer to the layer including metal;

after contacting the third layer to the layer including metal, forming a mechanical bonding material between the first substrate and the second substrate, wherein the forming a mechanical bonding material includes applying heat to the third layer and the layer including metal, wherein the bonding material includes a metal of the layer including metal and material of the third layer;

forming a semiconductor device over the first substrate which is surrounded by a ring including the layer including metal; and

forming a cavity in the second substrate, wherein the step of contacting is further characterized as aligning the cavity with the semiconductor device.

15. The method of claim 14, wherein the step of forming the semiconductor device is further characterized by the semiconductor device being a micro electromechanical system (MEMS) device.

16. A method for providing a seal between a first substrate and a second substrate, comprising:

contacting the first substrate to the second substrate through a bonding stack, wherein the bonding stack comprises;

a first layer comprising silicon;

a second layer comprising germanium and silicon in contact with the first layer;

a third layer comprising germanium in contact with the second layer; and

a layer including metal in contact with the third layer;

applying heat and pressure to the bonding stack so that the bonding stack becomes a bond between the first and second substrates;

forming a semiconductor device on the first substrate, wherein the bonding stack surrounds the semiconductor device.

17. The method of claim 16, wherein the step of contacting is further characterized by the layer including metal being formed over the first substrate and the first layer being formed over the second substrate.

18. The method of claim 16, wherein the step of contacting is further characterized by the first, second, and third layers being polycrystalline.

19. The method of claim 16 wherein the step of contacting is further characterized by the layer including metal comprising aluminum.

20. The method of claim 16, wherein the step of contacting is further characterized by the first and second layers being less thick than the third layer.

21. The method of claim 16 wherein the applying heat includes applying heat at a temperature of 500 C. or less.

22. The method of claim 16, wherein the third layer comprises polycrystalline germanium.

23. The method of claim 16, wherein the bond hermetically seals the semiconductor device between the first substrate and the second substrate.

24. The method of claim 16, the method further comprising after applying the heat and pressure to the bonding stack, singulating the first substrate and the second substrate into a plurality of die with each die including a semiconductor device hermetically sealed between a portion of the first substrate and a portion of the second substrate with a bond formed during the applying the heat and pressure.