FinFET structure with multiply stressed gate electrode

• US 8,058,157 B2
• Filed: 07/20/2009
• Issued: 11/15/2011
• Est. Priority Date: 11/30/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Luo, Zhijiong, Zhu, Huilong
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/505,894
• Publication Number:
  US 20090280626A1
• Time in Patent Office: 848 Days
• Field of Search: 438/479, 438/517, 438/527, 438/528, 438/530, 438/532, 438/533
• US Class Current: 438/517
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different than the first stress in a second region located further from the semiconductor fin. The semiconductor fin may also be aligned over a pedestal within the substrate. The semiconductor structure is annealed under desirable stress conditions to obtain an enhancement of semiconductor device performance.

Claims

1. A method for fabricating a structure comprising:

forming a semiconductor fin over a substrate; and

forming a gate electrode over the semiconductor fin, the gate electrode having a first stress in a first region located nearer the semiconductor fin and a second stress which is different than the first stress in a second region located further from the semiconductor fin, wherein said forming the gate electrode comprises providing a patterned gate electrode conductor material over said semiconductor fin, ion implanting into said patterned gate electrode conductor material to form a partially amorphized gate electrode comprising an unamorphized sub-layer located nearer the semiconductor fin and an amorphized sub-layer located further from the semiconductor fin, forming a stress imparting layer atop the partially amorphized gate electrode, performing a thermal annealing, said thermal annealing recrystallizes said amorphized sub-layer, while introducing stress to the recrystallized sub-layer forming the second region of the gate electrode, and removing the stress imparting layer, and wherein said unamorphized sub-layer provides said first region of the gate electrode.

2. The method of claim 1 wherein the substrate is a semiconductor-on-insulator substrate.

3. The method of claim 1 wherein the semiconductor fin comprises a semiconductor material selected from the group consisting of Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, other III-V or II-VI compound semiconductor materials and organic semiconductor materials.

4. The method of claim 1 wherein the first stress and the second stress provide a gradient of stress.

5. The method of claim 1 wherein the first stress and the second stress are of opposite type.

6. The method of claim 1 wherein the semiconductor fin is formed over a raised portion of the substrate.

7. The method of claim 1 wherein the semiconductor fin is formed aligned over a raised portion of the substrate.

8. The method of claim 1 wherein said ion implanting comprises a dose of an amorphizing ion.

9. The method of claim 8 wherein said amorphizing ion comprises Ge.

10. The method of claim 8 wherein said dose is from 1e18 to 1e22 atoms per cubic centimeter.

11. The method of claim 8 wherein said ion implanting is performed at an angle from 30°

to 45°

relative to an upper horizontal surface of the substrate.

12. The method of claim 1 further comprising forming a pad dielectric layer between the partially amorphized gate electrode and the stress inducing layer.

13. The method of claim 1 wherein said thermal annealing is performed at a temperature from 1000°

C. to 1200°

C.

14. The method of claim 10 wherein said thermal annealing is performed for a time period of from 2 to 6 hours.

15. The method of claim 1 wherein said removing the stress inducing layer comprises etching in aqueous phosphoric acid.

16. The method of claim 1 wherein said removing the stress inducing layer comprises etching in aqueous hydrofluoric acid.

17. The method of claim 1 further comprising a patterned hard mask on an upper surface of the semiconductor fin, said patterned hard mask separates a portion of the gate electrode over said semiconductor fin from said semiconductor fin.