Dynamic Schottky barrier MOSFET device and method of manufacture

• US 8,058,167 B2
• Filed: 09/28/2009
• Issued: 11/15/2011
• Est. Priority Date: 10/22/2003
• Status: Expired due to Fees

• Current Assignee: Avolare2 LLC
• Original Assignee: Avolare2 LLC
• Inventors: Snyder, John P., Larson, John M.
• Primary Examiner(s): Thomas; Tom
• Assistant Examiner(s): REAMES, MATTHEW L
• Application Number:
  US12/568,655
• Publication Number:
  US 20100015802A1
• Time in Patent Office: 778 Days
• Field of Search: 438/664, 438/655, 438/651, 257/E21.159
• US Class Current: 438/664
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0895 Tunnel injectors
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

Claims

1. A method of manufacturing a device for regulating a flow of electrical current, the method comprising:

creating exposed areas on a semiconductor substrate in an area proximal to a gate electrode;

etching the exposed areas using an at least partially isotropic etch to create an etched area that extends to an undercut area partially under the gate;

depositing and thermally annealing a film of a first metal with the semiconductor substrate such that a Schottky or Schottky-like source electrode and a Schottky or Schottky-like drain electrode are formed on the undercut area using the first metal;

removing a portion of the first metal that is not in the undercut area;

blanket depositing a film of a second metal on the etched area of the semiconductor substrate;

reacting the second metal such that a continued Schottky or Schottky-like source electrode and a continued Schottky or Schottky-like drain electrode are formed next to the undercut area using the second metal.

2. The method of claim 1, wherein the etching includes using an etch having a lateral etch rate of from approximately one-tenth to ten times of a vertical etch rate.

3. The method of claim 1, wherein the etching includes using an etch having approximately equal lateral and vertical etch rates.

4. The method of claim 1, wherein the etching includes using an etch having lateral and vertical etch rates such that a channel width of the device is reduced by between approximately 1 percent and 50 percent.

5. The method of claim 1, further including heating the semiconductor substrate during the depositing in order to encourage surface diffusion of metal atoms along a surface of the semiconductor substrate.

21. The method of claim 1, wherein the reacting includes thermal annealing.

6. A method of manufacturing a MOSFET device for regulating a flow of electrical current, the method comprising:

providing a gate on a semiconductor substrate;

creating an exposed area on the semiconductor substrate in an area proximal to the gate;

etching the exposed area on the semiconductor substrate to create an etched area that extends to an undercut area partially under the gate;

blanket depositing a film of a first metal on the etched area of the semiconductor substrate;

removing a portion of the first metal that is not in the undercut area;

blanket depositing a film of a second metal on the etched area of the semiconductor substrate;

reacting both the first metal and the second metal with the semiconductor substrate such that a Schottky or Schottky-like source electrode and a Schottky or Schottky-like drain electrode are formed in the undercut area using the first metal, and a continued Schottky or Schottky-like source electrode and a continued Schottky or Schottky-like drain electrode are formed next to the undercut area using the second metal.

7. The method of claim 6, further including heating the semiconductor substrate during the depositing in order to encourage surface diffusion of metal atoms along a surface of the semiconductor substrate under the gate.

8. The method of claim 6, wherein the etching further includes using an etch having lateral and vertical etch rates such that a channel width of the device is reduced by between approximately 1 percent and 50 percent.

10. The method of claim 6, wherein the etching includes using an etch having a lateral etch rate of from approximately one-tenth to ten times of a vertical etch rate.

11. The method of claim 6, wherein the etching includes using an etch having approximately equal lateral and vertical etch rates.

12. The method of claim 6, wherein the providing of the gate-further includes:

providing a thin insulating layer on the semiconductor substrate;

depositing a conducting film on the thin insulating layer;

patterning and etching the conducting film to form a gate electrode; and

forming at least one insulating layer on at least one sidewall of the gate electrode.

13. The method of claim 6, further comprising removing unreacted metal from the MOSFET device after forming the Schottky or Schottky-like source and drain electrodes and the continued Schottky or Schottky-like source and drain electrodes.

14. The method of claim 6, wherein the reacting includes thermal annealing.

15. The method of claim 6, wherein the source electrode and the drain electrode are formed from a member of the group consisting of:

Platinum Silicide, Palladium Silicide and Iridium Silicide, and channel dopants in the semiconductor substrate are selected from the group consisting of;

Arsenic, Phosphorous, and Antimony.

16. The method of claim 6, wherein the source electrode and the drain electrode are formed from a member of the group consisting of the rare-earth silicides, and channel dopants in the semiconductor substrate are selected from the group consisting of Boron, Indium, and Gallium.

17. The method of claim 6, wherein a Schottky or Schottky-like contact is formed at least in areas adjacent to a channel between the source electrode and the drain electrode.

18. The method of claim 6, wherein an entire surface of the of the source electrode and an entire surface of the drain electrode form a Schottky or Schottky-like contact with the semiconductor substrate.

19. The method of claim 6, wherein before the providing of the gate-the method further includes introducing dopants into the semiconductor substrate, and wherein the introducing of dopants into the semiconductor substrate includes forming a channel dopant concentration that varies significantly in a vertical direction and is generally constant in a lateral direction.

20. The method of claim 6, wherein the Schottky or Schottky-like source electrode and the Schottky or Schottky-like drain electrode are formed of a first conductive material and the continued Schottky or Schottky-like source electrode and the continued Schottky or Schottky-like drain electrode are formed of a second conductive material that is different than the first conductive material.

9. A method of manufacturing a MOSFET device for regulating a flow of electrical current, the method comprising:

providing a gate on a semiconductor substrate;

creating exposed areas on the semiconductor substrate in an area proximal to the gate;

etching the exposed areas to create etched areas that extend to undercut areas partially under the gate;

depositing a film of a first metal in the etched areas of the semiconductor substrate; and

reacting the first metal with the semiconductor substrate such that a Schottky or Schottky-like source electrode and a Schottky or Schottky-like drain electrode are formed;

wherein the etching includes using an at least partially isotropic etch;

wherein before the reacting the method further includes;

removing a portion of the first metal that is not in the undercut areas, and blanket depositing a second metal on the etched area of the semiconductor substrate; and

wherein the reacting of the first metal further includes reacting the second metal with the semiconductor substrate such that the Schottky or Schottky-like source electrode and the Schottky or Schottky-like drain electrode are formed in the undercut areas using the first metal, and a continued Schottky or Schottky-like source electrode and a continued Schottky or Schottky-like drain electrode are formed next to the undercut areas using the second metal.