Semiconductor device

• US 8,058,682 B2
• Filed: 01/08/2008
• Issued: 11/15/2011
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US11/971,096
• Publication Number:
  US 20080191307A1
• Time in Patent Office: 1,407 Days
• Field of Search: 257328-346, 257/E21.418, 257/E29.183
• US Class Current: 257/328
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/2003 characterised by the substrate
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66537 : using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor structure includes a number of semiconductor regions, a pair of dielectric regions and a pair of terminals. The first and second regions of the structure are respectively coupled to the first and second terminals. The third region of the structure is disposed between the first and second regions. The dielectric regions extend into the third region. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the structure. The electrical characteristic of the structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types. The structure optionally includes a fourth region that extends into the third region, and surrounds a portion of the pair of dielectric regions. The interface region between the dielectric regions and the fourth region includes intentionally introduced charges.

Claims

1. A semiconductor structure comprising:

a first semiconductor region coupled to a first terminal of the structure;

a second semiconductor region coupled to a second terminal of the structure;

a third semiconductor region disposed between the first and second semiconductor regions; and

at least first and second dielectric regions extending a first distance along a depth of the third semiconductor region, wherein said first and second semiconductor regions are of opposite conductivity types, and wherein the at least first and second dielectric regions or an interface region between each of said at least first and second dielectric regions and said third semiconductor regions includes intentionally introduced charges.

2. The semiconductor structure of claim 1, wherein said at least first and second dielectric regions extend into the first and second semiconductor regions.

3. The semiconductor structure of claim 1, wherein an integrated density of doping impurities in the third semiconductor region along a line parallel to a surface of the at least first and second dielectric regions ranges from about 1×

10¹²/cm² to about 5×

10¹²/cm².

4. The semiconductor structure of claim 1, wherein each of the at least first and second dielectric regions further comprises first and second materials.

5. The semiconductor structure of claim 1, wherein said intentionally introduced charges are implanted positive charges.

6. The semiconductor structure of claim 1, wherein said intentionally introduced charges are implanted negative charges.

7. The semiconductor structure of claim 4, wherein the second material in each of the at least first and second dielectric regions comprises aluminum fluoride.

8. The semiconductor structure of claim 4, wherein each of the at least first and second dielectric regions further comprises a third material, said third material being a dielectric material.

9. The semiconductor structure of claim 8, wherein the first and third materials in each dielectric region are the same material.

10. The semiconductor structure of claim 1, wherein said first and second semiconductor regions are respectively p+ type and n+ type regions, said first and second terminals are respectively anode and cathode terminals, and said third semiconductor region is a p-type semiconductor region.

11. The semiconductor structure of claim 10, wherein said third semiconductor region is formed above the second semiconductor region, and said first region is formed above the third semiconductor region.

12. The semiconductor structure of claim 1, wherein said first and second semiconductor regions are respectively p+ type and n+ type regions, said first and second terminals are respectively anode and cathode terminals, and said third semiconductor region is an n-type semiconductor region.

13. The semiconductor structure of claim 12, wherein said third semiconductor region is formed above the second semiconductor region, and said first semiconductor region is formed above the third semiconductor region.

14. The semiconductor structure of claim 1, wherein said at least first and second dielectric regions are isolated from one another.

15. The semiconductor structure of claim 1, wherein said semiconductor structure further comprises a fourth semiconductor region disposed between the second and the third semiconductor regions, said second and fourth semiconductor regions being of the same conductivity type.

16. The semiconductor structure of claim 1, wherein said first and second semiconductor regions are respectively n+ type and p+ type regions, said first and second terminals are respectively cathode and anode terminals, and said third semiconductor region is a p-type region.

17. The semiconductor structure of claim 10, wherein said third semiconductor region is formed above the second semiconductor region and said first semiconductor region is formed above the third semiconductor region.

18. The semiconductor structure of claim 1, wherein said first and second semiconductor regions are respectively n+ type and p+ type regions, said first and second terminals are respectively cathode and anode terminals, and said third semiconductor region is an n-type region.

19. The semiconductor structure of claim 10, wherein said third semiconductor region is formed above the second semiconductor region, and said first semiconductor region is formed above the third semiconductor region.

20. The semiconductor structure of claim 10, wherein each of said at least first and second dielectric regions is tapered so as to have a larger width near one end of the dielectric region than another end of the dielectric region.

21. The semiconductor structure of claim 10, wherein said first, second and third semiconductor regions are formed along the same surface of a semiconductor substrate in which the semiconductor structure is formed.

22. The semiconductor structure of claim 21, further comprising:

a fourth semiconductor region in which the second semiconductor region is formed, said third region being adjacent to said first and fourth semiconductor regions.

23. The semiconductor structure of claim 22, wherein said first semiconductor region is a p+ type semiconductor region, said second semiconductor region is an n+ type semiconductor region, said third semiconductor region is a p-type semiconductor region and said fourth semiconductor region is an n-type semiconductor region.

24. The semiconductor structure of claim 22, wherein said first semiconductor region is a p+-type semiconductor region, said second semiconductor region is an n+-type semiconductor region, said third semiconductor region is an n-type region and said fourth semiconductor region is a p-type region.

25. A semiconductor structure comprising:

a first semiconductor region coupled to a first terminal of the structure;

a second semiconductor region coupled to a second terminal of the structure;

a third semiconductor region disposed between the first and second regions;

a fourth semiconductor region extending a first distance along a depth of the third semiconductor region and having a conductivity type opposite a conductivity type of the third semiconductor region, said fourth semiconductor region being adjacent the first and second; and

at least first and second dielectric regions extending a second distance along a depth of the third semiconductor region, wherein said first and second semiconductor regions are of opposite conductivity types, wherein said fourth semiconductor region surrounds a portion of the at least first and second dielectric regions, and wherein said at least first and second dielectric regions or an interface region between each of said at least first and second dielectric regions and said fourth semiconductor regions includes intentionally introduced charges which are immobile at typical device operating temperatures.

26. The semiconductor structure of claim 25, wherein said at least first and second dielectric regions extend into the first and second semiconductor regions.

27. The semiconductor structure of claim 25, wherein each of the at least first and second dielectric regions further comprises first and second materials.

28. The semiconductor structure of claim 25, wherein said intentionally introduced charges are implanted positive charges.

29. The semiconductor structure of claim 25, wherein said intentionally introduced charges are implanted negative charges.

30. The semiconductor structure of claim 27, wherein the second material in each of the at least first and second dielectric regions comprises aluminum fluoride.

31. The semiconductor structure of claim 27, wherein each of the at least first and second dielectric regions further comprises a third material, said third material being a dielectric material.

32. The semiconductor structure of claim 31, wherein the first and third materials in each dielectric region are the same material.

33. The semiconductor structure of claim 25, wherein said first and second semiconductor regions are respectively p+ type and n+ type semiconductor regions, said first and second terminals are respectively anode and cathode terminals, and said third semiconductor region is a p-type region.

34. The semiconductor structure of claim 33, wherein said third semiconductor region is formed above the second semiconductor region and said first semiconductor region is formed above the third semiconductor region.

35. The semiconductor structure of claim 25, wherein said first and second semiconductor regions are respectively p+ type and n+ type semiconductor regions, said first and second terminals are respectively anode and cathode terminals, and said third semiconductor region is an n-type semiconductor region.

36. The semiconductor structure of claim 35, wherein said third semiconductor region is formed above the second semiconductor region and said first semiconductor region is formed above the third semiconductor region.

37. The semiconductor structure of claim 25, wherein said at least first and second dielectric regions are isolated from one another.

38. The semiconductor structure of claim 25, wherein said semiconductor structure further comprises a fifth semiconductor region disposed between the second, the third, and the semiconductor fourth regions, said second and fifth semiconductor regions being of the same conductivity type.

39. The semiconductor structure of claim 25, wherein said first and second semiconductor regions are respectively n+ type and p+ type semiconductor regions, said first and second terminals are respectively cathode and anode terminals, and said third region is a p-type semiconductor region.

40. The semiconductor structure of claim 39, wherein said third semiconductor region is formed above the second semiconductor region, and said first semiconductor region is formed above the third semiconductor region.

41. The semiconductor structure of claim 25, wherein said first and second semiconductor regions are respectively n+ type and p+ type semiconductor regions, said first and second terminals are respectively cathode and anode terminals, and said third semiconductor region is an n-type region.

42. The semiconductor structure of claim 41, wherein said third semiconductor region is formed above the second semiconductor region and said first semiconductor region is formed above the third semiconductor region.

43. The semiconductor structure of claim 25, wherein each of said at least first and second dielectric regions is tapered so as to have a larger width near one end of the dielectric region than another end of the dielectric region.

44. The semiconductor structure of claim 25, wherein said first, second and third semiconductor regions are formed along the same surface of a semiconductor substrate in which the semiconductor structure is formed.

45. The semiconductor structure of claim 44, further comprising:

a fifth semiconductor region in which the second semiconductor region is formed, said third semiconductor region being adjacent to said first and fifth semiconductor regions.

46. The semiconductor structure of claim 45, wherein said first semiconductor region is a p+ type semiconductor region, said second semiconductor region is an n+ type semiconductor region, said third semiconductor region is a p-type semiconductor region and said fourth semiconductor region is an n-type semiconductor region.

47. The semiconductor structure of claim 45, wherein said first semiconductor region is a p+-type semiconductor region, said second semiconductor region is an n+-type semiconductor region, said third semiconductor region is an n-type semiconductor region and said fourth semiconductor region is a p-type semiconductor region.